IC可测性与3D芯片测试技术的分析  

Analysis of IC Testability and 3D Chip Testing Technology

作　　者：张峰 袁欣欣[1,2,3] 李拓 苏康 杜雅楠[1,2,3] 刘凯 满宏涛 邹晓峰 ZHANG Feng;YUAN Xinxin;LI Tuo;SU Kang;DU Yanan;LIU Kai;MAN Hongtao;ZOU Xiaofeng(State Key Laboratory of High-end Server&Storage Technology Inspur Group Company Limited,Beijing 100085,China;Shandong Inspur Artificial Intelligence Research Institute Co.,Ltd.,Shandong 250101,China;Inspur Electronic Information Industry Co.,Ltd,Beijing 100085,China)

机构地区：[1]高效能服务器和存储技术国家重点实验室,北京100085 [2]山东浪潮人工智能研究院有限公司,山东250101 [3]浪潮电子信息产业股份有限公司,北京100085

出　　处：《电子技术（上海）》2023年第7期6-8,共3页Electronic Technology

摘　　要：阐述系统级芯片SoC的可测性技术DFT,在系统测试中发挥着极其重要的作用。DFT技术主要包括扫描测试和内建自测试BIST,探讨测试数据压缩技术、低功耗测试技术、并发在线测试中的DFT测试技术,以及3D IC测试技术的原理、存在的问题和发展前景。DFT测试技术实现低功耗、低测试成本、测试时间短、高故障覆盖率和高测试效率。This paper describes the Design for Test DFT of System on Chip SoC,which plays an extremely important role in system testing.DFT technology mainly includes scanning test and Builtin self-test BIST.It discusses test data compression technology,low-power test technology,DFT test technology in concurrent online test,and the principle,existing problems and development prospects of 3D IC test technology.DFT testing technology achieves low power consumption,low testing cost,short testing time,high fault coverage,and high testing efficiency.

关 键 词：集成电路测试 系统级芯片 扫描测试 测试数据压缩 

分 类 号：TN407[电子电信—微电子学与固体电子学]