基于指令生成约束的RISC-V测试序列生成方法  

A RISC-V Test Sequences Generation Method Based on Instruction Generation Constraints

作　　者：刘鹏[1] 胡文超 刘德启 韩晓霞[1] 刘扬帆 LIU Peng;HU Wenchao;LIU Deqi;HAN Xiaoxia;LIU Yangfan(College of Information Science&Electronic Engineering,Zhejiang University,Hangzhou 310027,China;HEXIN Technologies Co.,Ltd.,Guangzhou 510725,China)

机构地区：[1]浙江大学信息与电子工程学院,杭州310027 [2]合芯科技有限公司,广州510725

出　　处：《电子与信息学报》2023年第9期3141-3149,共9页Journal of Electronics & Information Technology

摘　　要：为了避免处理器受到指令缺陷的威胁,该文提出基于指令生成约束的RISC-V测试序列生成方法,构建测试指令序列生成框架,实现测试指令生成及指令缺陷检测,解决现有测试指令序列生成方法约束定义困难和收敛速度慢的问题。在该方法中,首先,根据指令集架构规范和指令验证需求定义指令生成约束,包括指令格式约束、通用功能覆盖约束和特殊功能覆盖约束,以解决随着指令数量增多约束定义的困难,提高可复用性;然后,定义启发式搜索策略,通过统计覆盖信息,加快覆盖率收敛速度;最后,基于启发式搜索策略构造求解算法,实现满足指令生成约束的测试序列生成。实验结果表明,与现有方法相比,在覆盖所有指令验证需求的前提下,结构覆盖率和数值覆盖率的收敛时间分别减少了85.62%和57.64%。利用该框架对开源处理器进行检测,可以定位到在处理器译码和执行阶段引入的指令缺陷,为处理器指令缺陷检测提供了有效的方法。In order to avoid the threat of instruction defects to the processor,this paper proposes a RISC-V test sequence generation method based on instruction generation constraints.A test instruction sequence generation framework is constructed based on this method to achieve test instruction generation and instruction defect detection,while addressing the challenges in defining constraints and slow convergence speed in existing test instruction sequence generation methods.Firstly,the instruction generation constraints are defined according to the instruction set architecture specification and instruction verification requirements.These constraints include instruction format constraints,general coverage constraints,and particular coverage constraints,aiming to solve the challenges in defining constraints as the number of instructions increases and improve reusability.Then,a heuristic search strategy is applied to accelerating the convergence rate of coverage by utilizing statistical coverage information.Finally,a solving algorithm is constructed based on the heuristic search strategies to generate test sequences that satisfy the instruction generation constraints.The experimental results show that,compared with the state-of-the-art methods,the convergence time of structural coverage is reduced by 85.62%and numerical coverage is reduced by 57.64%,under the premise of covering all instruction verification requirements.By using this framework to detect open-source processor,instruction defects introduced in the processor decoding and execution stages can be located,providing an efficient method for detecting processor instruction defects.

关 键 词：处理器 RISC-V 指令缺陷检测 约束指令生成 

分 类 号：TN407[电子电信—微电子学与固体电子学]