基于CML结构的高速4/5双模分频器  

High-speed 4/5 Dual-mode frequency divider based on CML structure

作　　者：范海宇 沈剑 谢至瑶 FAN Hai-yu;SHEN Jian;XIE Zhi-yao(School of Internet of Things Engineering,Jiangnan University;China Electronics Technology Group Corporation)

机构地区：[1]江南大学物联网工程学院 [2]中国电子科技集团公司第五十八研究所

出　　处：《中国集成电路》2023年第8期34-38,共5页China lntegrated Circuit

摘　　要：为了满足射频系统高速的需求,在0.13μm SiGe BiCMOS工艺下,基于电流模逻辑(current mode logic,CML),设计了一款高速4/5双模分频器。在传统电路的基础上提出了嵌入逻辑门技术和主次锁存器尺寸非对称技术来减少路径的延时,提高双模分频器的最高工作频率。工作电源电压3.3 V,输入信号摆幅400 mV下,经过后仿真验证,工作频率可覆盖4 GHz~24 GHz。In order to meet the high-speed requirements of RF systems,a high-speed 4/5 dual-mode frequency divider is designed based on current mode logic(CML)in a 0.13um SiGe BiCMOS process.The embedded logic gate technique and asymmetric primary and secondary latch sizes are proposed on the basis of the conventional circuit to reduce the path delay and increase the maximum operating frequency of the dual-mode divider.The operating frequency can be covered from 4GHz to 24GHz after post-simulation verification with an operating supply voltage of 3.3V and an input signal swing of 400mV.

关 键 词：CML 高速 双模分频器 相位噪声 

分 类 号：TN772[电子电信—电路与系统]