一种基于55nm工艺的超前进位加法器设计  

A Design of Carry-Ahead Adder Based on 55nm Process Technology

作　　者：周冉冉 周文宸 王永 ZHOU Ran-ran;ZHOU Wen-chen;WANG Yong(School of Microelectronics,Shandong university)

机构地区：[1]山东大学微电子学院

出　　处：《中国集成电路》2023年第8期49-53,共5页China lntegrated Circuit

摘　　要：加法器作为数字电路中的重要组件,其计算速度对系统性能至关重要。本文对加法器电路进行了深入研究,基于4进制Kogge-Stone树结构和多相时钟控制改进后的多米诺动态电路,设计了一种64位超前进位加法器,并完成全定制版图设计。该加法器采用55nm CMOS工艺,在3.7 GHz的时钟频率下,关键路径延时为372 ps,平均功耗为24.47 mW,功耗延时积为9.1 pJ,版图总面积约为29482μm2。这些结果显示,所提出的设计方案在性能方面取得了显著的改进。它不仅提高了加法器电路的计算速度,还有效降低了功耗和占用的芯片面积。Adders,as vital components in digital circuits,play a crucial role in determining system performance.This paper extensively investigates the adder circuit and proposes a design scheme based on a 4-bit Kogge-Stone tree structure.The design incorporates an improved domino dynamic circuit utilizing multiphase clocking and is implemented through fully custom layout design.The design employs a 55 nm process technology with a clock frequency of 3.7 GHz.The critical path delay is measured at 372 ps,and the average power consumption is 24.47 mW,resulting in a power-delay product of 9.1 pJ.The total layout area occupies a pproximately 29482μm2.These results demonstrate significant improvements in performance achieved by the proposed design scheme.It not only enhances the computational speed of the adder circuit but also effectively reduces power consumption and chip area occupation.

关 键 词：加法器 Kogge-Stone 超前进位 

分 类 号：TN405[电子电信—微电子学与固体电子学] TN791