Cadence先进封装EDA工具高效赋能CoWoS-S硅中介层设计和签核  

Energizing the silicon interposer design and sign-off with cutting-edge design tools from Cadence

作　　者：谷雨 徐兴隆 陈恺立 刘华宝 孙晨 王海三 祁芮 徐国治 Ed GU;Jerry XU;Cary CHEN;Louis LIU;SUN Chen;WANG Hai-san;QI Rui;XU Guo-zhi(MetaX Integrated Circuits(Shanghai)Co.,Ltd.;Cadence Design Systems,Inc.)

机构地区：[1]沐曦集成电路(上海)有限公司 [2]上海楷登电子科技有限公司

出　　处：《中国集成电路》2023年第10期76-82,共7页China lntegrated Circuit

摘　　要：随着摩尔定律的放缓,通过制程微缩来提高芯片性能越来越难,基于芯粒集成的先进封装方案的重要性随之日益显现。尤其是在一些高算力芯片产品的设计上,采用芯粒集成已逐渐成为设计者们一个绕不开的性能提高手段。在2.5D先进封装方案中,CoWoS-S(chip on wafer on substrate)封装因其高带宽、低延迟及丰富的成功量产案例而被广泛应用于片上系统芯片(SoC-system on chip)与高带宽内存(HBM-high bandwidth memory)的互连。然而,在CoWoS-S技术的硅中介层设计过程中,设计人员将面临严苛的信号完整性与电源完整性的综合挑战。为了解决这些挑战,Cadence作为EDA领域的创新者和领导者,开发了完整的EDA解决方案,以协助设计人员完成硅中介层的设计及签核任务。本文将介绍如何利用Cadence EDA解决方案来高效率地实现CoWoS-S硅中介层的设计与签核,内容聚焦于大电流区域的电源完整性设计以及HBM互连区域的信号完整性设计。With the Moore’s Law slowing down,chiplet based packaging solution has been increasingly appealing for advanced computing applications.With more than a decade of development and evolution,the CoWoS-S technology has become one of the most popular 2.5D integration packaging solutions,given its superior advantages on high band-width signal transmissions,low latency connections,smooth logic die to high bandwidth memory(HBM)communica-tions,and the most importantly,its numerous high volume manufacturing successes.However,challenges lie in front of designers who are obligated to deliver a high-density redistribution layer(RDL)silicon interposer design with the pursuit of reduced design cycle time and satisfactory power integrity(PI)and signal integrity(SI)performances.As the pioneer in the design tool industry,Cadence has been putting continuous efforts in developing new design method-ologies and efficient design tools to empower the 2.5D package design.In this article,we will present a systematic design flow with the aid of Cadence tools that enable a more vigorous interposer design process.In addition,methods to achieve desired PI performance for core area with high current demands and SI performance for connections between the logic die and memories under given crosstalk and capacitive parasitic effects will be illustrated.The criti-cality of advanced Cadence tools and design methodology in solving the challenges related to the latest CoWoS-S technology will hence be shown.

关 键 词：CoWoS-S 硅中介层 深沟电容 HBM Integrity 3D-IC平台 XcitePI Extraction CLARITY Optimality Explorer 

分 类 号：TN405[电子电信—微电子学与固体电子学]