一种低噪声全差分电荷泵型锁相环的实现  

Implementation of a Low Noise Fully Differential Charge Pump Phase Locked Loop

作　　者：师勇阁 胡勇华 高秋辰[1] SHI Yongge;HU Yonghua;GAO Qiuchen(National Supercomputing Center in Zhengzhou,Zhengzhou University,Zhengzhou,450001,CHN;School of Computer Science and Engineering,Hunan University of Science and Technology,Xiangtan,Hunan,411201,CHN)

机构地区：[1]郑州大学国家超级计算郑州中心,郑州450001 [2]湖南科技大学计算机科学与工程学院,湖南湘潭411201

出　　处：《固体电子学研究与进展》2023年第4期347-352,共6页Research & Progress of SSE

基　　金：湖南省教育厅科学研究项目(20B242)。

摘　　要：采用HHGrace 180 nm CMOS工艺实现了一款低噪声全差分电荷泵型锁相环,可为物理层芯片提供精确且稳定的时钟信号。鉴频鉴相器和分频器采用电流模逻辑电路构成基本单元,提高了锁相环的工作速度;设计了一种改进型差分电荷泵,引入共模反馈使电荷泵输出电压的静态工作点更加稳定,提高了锁相环的相位噪声性能。测试结果表明,该锁相环功耗小于24 mW,芯片面积为510μm×620μm,锁定时间小于2.5μs,相位噪声为-108 dBc/Hz@100 kHz、-113 dBc/Hz@1 MHz。A low-noise fully differential charge-pump phase-locked loop(PLL)was implemented by HHGrace 180 nm CMOS technology,which could provide accurate and stable clock signals for physical layer chips.The current mode logic circuit was used as the basic unit of the phase frequency detector and the frequency divider to improve the working speed of the phase-locked loop.An improved differential charge pump with common mode feedback was designed to make the static working point of the charge pump output voltage more stable and improve the phase noise performance of the phase-locked loop.The test results show that the power consumption of the PLL is less than 24 mW and the chip area is 510μm×620μm.The locking time is less than 2.5μs.The phase noise are-108 dBc/Hz@100 kHz and-113 dBc/Hz@1 MHz.

关 键 词：全差分电荷泵 电流模逻辑 锁相环 压控振荡器 低噪声 

分 类 号：TN911.8[电子电信—通信与信息系统]