可重构阵列处理器上HEVC流水线并行化设计与实现  

Design and implementation of pipelined parallelization HEVC based on reconfigurable array processor

作　　者：赵静 蒋林 朱筠 谢晓燕 杨坤 崔馨月 ZHAO Jing;JIANG Lin;ZHU Yun;XIE Xiaoyan;YANG Kun;CUI Xinyue(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;School of Safety Science and Engineering,Xi’an University of Science and Technology,Xi’an 710600,China;School of Computer Science,Xi’an University of Posts and Telecommunications,Xi’an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安科技大学安全科学与工程学院,陕西西安710600 [3]西安邮电大学计算机学院,陕西西安710121

出　　处：《传感器与微系统》2023年第10期95-98,102,共5页Transducer and Microsystem Technologies

基　　金：国家自然科学基金资助项目(61834005,61772417,61802304,61602377,61634004);陕西省重点研发计划资助项目(2021GY029)。

摘　　要：为了解决新一代高效视频编码(HEVC)标准中计算复杂度大幅增加导致的编码速度降低问题和专用硬件实现编码器灵活性差的问题,提出了一种基于可重构阵列处理器的HEVC流水线并行化实现方法。该方法将编码块的处理过程划分为不同的流水线等级,根据算法特性设计流水线并行映射方案,并基于可重构阵列处理器的握手机制设计流水线调度方式,使得同一时刻各流水级并行处理不同的编码块,从而加速视频图像的编码过程。实验结果表明:该方案与非流水线实现相比,编码时间减少了约66%;与在现场可编程门阵列(FPGA)上通过模式决策并行化实现加速的方案相比,编码时间减少了18%;与HEVC官方测试模型HM16.8相比,平均PSNR值增加了0.0219 dB。In order to solve the problem of reduced coding speed caused by the substantial increase in computational complexity in high efficiency video coding(HEVC)and poor flexibility of encoder implemented by special hardware,a parallel implementation method of pipelined HEVC based on a reconfigurable array processor is proposed.This method divides the processing of the encoding block into different pipeline levels,and a pipeline parallel mapping scheme is designed according to the characteristics of the algorithm.And the pipeline scheduling mode is designed based on the handshake mechanism of reconfigurable array processor,so that different coding blocks are processed in parallel at each pipeline level at the same time,so as to accelerate the coding process of video images.Experimental results show that compared with the non-pipelined solution,the encoding time is reduced by about 66%;compared with the scheme that realizes acceleration in field programmable gate array(FPGA)through mode decision parallelization,the encoding time is reduced by 18%;compared with the official HEVC test model HM16.8,the average PSNR value is increased by 0.0219 dB.

关 键 词：高效视频编码 流水线 阵列处理器 并行化 可重构 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]