一种高速双极工艺的ESD设计优化  

ESD Design Optimization of a High Speed Bipolar Process

作　　者：徐佳丽[1] 杨阳[1] 周远杰 XU Jia-li;YANG Yang;ZHOU Yuan-jie(Sichuan Institute of Solid State Circuits,China Electronics Technology Group Corp,Chongqing 400060)

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《环境技术》2023年第8期113-117,共5页Environmental Technology

摘　　要：针对国内某高速双极工艺的静电保护能力瓶颈问题,我们分析了原标准库静电结构的不足,研究了三极管的击穿特性,提出一种二极管与CE结并联的新型保护结构,并对版图进行了优化,工艺流片结果表明其满足2kV(HBM)要求。该结构近几年已成功应用于多个高速运算放大器、电压比较器、宽带检波器等项目,由此完善了工艺抗静电平台的建设。For the bottleneck problem of electrostatic protection ability of domestic high speed bipolar process,we have analyzed the disadvantage of the original standard structure,and studied the breakdown characterization of bipolar transistor.A novel ESD structure with diode and CE junction in parallel is proposed.By ESD layout optimization,we have achieved a 2 kv(HBM)circuit.In recent years,the structure have been successfully applied to many projects,such as high speed operational amplifier,voltage comparator and broadband detector,etc.Thus,electrostatic cell platform of the process is become better.

关 键 词：高速双极工艺 静电器件 ESD版图优化 

分 类 号：TN431[电子电信—微电子学与固体电子学]