基于SystemVerilog的浮点数约束生成器的研究与实现  

A Study and Implementation of a Floating-point Constraint Generator Based on SystemVerilog

作　　者：吴沁文[1] 王珊珊 WU Qinwen;WANG Shanshan(Nanjing Research Institute of Electronics Technology,Nanjing Jiangsu 210039,China)

机构地区：[1]南京电子技术研究所,江苏南京210039

出　　处：《现代雷达》2023年第7期75-82,共8页Modern Radar

摘　　要：SystemVerilog是专用于FPGA验证的语言,它的约束随机机制是支持FPGA随机测试的关键。然而,SystemVerilog语言仅提供了对整数类型的约束随机机制,这大大限制了需要使用浮点数随机激励的验证。文中设计了一种基于SystemVerilog的浮点数约束生成器,它通过转换机制,实现对浮点数的约束随机生成,从而将SystemVerilog的约束随机机制扩大到浮点数据类型,有效扩大了SystemVerilog约束随机验证的支持范围。SystemVerilog is a specialized language for FPGA verification,and its constrained random mechanism is the kernel to support FPGA random test.However,the SystemVerilog language only provides a constrained randomization mechanism for integral data types,which greatly limits the verification when floating-point random stimulus is needed.In this article,a floating-point constraint generator based on SystemVerilog is designed.It realizes the generation of constrained random floating-point number through a conversion mechanism,and thus extends the SystemVerilog constrained random mechanism to floating-point data types,which effectively expands the support range of SystemVerilog for constrained random test.

关 键 词：SystemVerilog语言 FPGA验证 约束随机 浮点数 

分 类 号：TN957.51[电子电信—信号与信息处理]