H.265/HEVC熵解码的分组并行流水线实现  

Parallel pipeline implementation of H.265/HEVC entropy decoding

作　　者：王世豪 周志刚 郭旭 殷先英 薛晓娜 赵靖宇 Wang Shihao;Zhou Zhigang;Guo Xu;Yin Xianying;Xue Xiaona;Zhao Jingyu(School of Electronics and Information,Hangzhou Dianzi University,Hangzhou 310018,China)

机构地区：[1]杭州电子科技大学电子信息学院,浙江杭州310018

出　　处：《电子技术应用》2023年第10期59-64,共6页Application of Electronic Technique

摘　　要：针对高效视频编码(H.265/HEVC)中CABAC熵解码模块的高资源消耗和数据依赖性,设计了一种多路并行的高效FPGA实现结构。根据不同类型语法元素特性,采用分组并行数据调度方法,减少数据处理等待时间和内部存储器访问次数,同时利用流水线技术实现运算加速。评估验证结果表明,熵解码模块吞吐量可以达到1.64位元/时钟周期,满足当下超高清视频实时解码的要求。To reduce the high resource consumption and high data dependency of the CABAC entropy decoding module in the new generation of High Efficiency Video Coding(H.265/HEVC),a multiple parallel CABAC decoding hardware circuit architecture is designed.According to the characteristics of different types of grammar elements in the decoding process,grouped parallel data scheduling is used to reduce the waiting time and the number of internal memory accesses for data processing,while pipeline technology is used to achieve acceleration of the arithmetic module.The design results show that the entropy decoding module has a throughput of 1.84 bins/clock cycle,meeting the current requirements for real-time decoding of UHD video.

关 键 词：H.265/HEVC CABAC FPGA 

分 类 号：TN919.81[电子电信—通信与信息系统]