SoC芯片的RomCode设计与FPGA验证研究  

Research on RomCode design of SoC chip and FPGA verification

作　　者：张梅娟[1] 张明月 杨楚玮 朱心杰 ZHANG Meijuan;ZHANG Mingyue;YANG Chuwei;ZHU Xinjie(The 58th Research Institute,CETC,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子设计工程》2023年第21期76-80,86,共6页Electronic Design Engineering

摘　　要：RomCode固化于SoC芯片内部且不可更改,除保证芯片上电时可进入到稳定工作状态之外,仍需满足芯片上电稳定后的不同应用场景和功能需求。该文针对多核ARM处理器SoC芯片,设计一种具备时钟控制、多核启动以及镜像搬移等功能的RomCode。为了确保RomCode设计的稳定性和正确性,基于Palladium与Haps完成FPGA原型验证。验证结果表明,该RomCode设计的功能正常且运行稳定,提高了芯片的流片成功率,加快了软件开发的进度,有效地支撑了SoC芯片其他模块的功能验证。RomCode is fixed inside the SoC chip and cannot be changed.In addition to ensuring that the SoC can work stably when powered on,it must meet different application scenarios and functional requirements after that.In this paper,a RomCode with clock control,multi-core startup and image migration is designed for the multi-core ARM processor SoC chip.To ensure the stability and correctness of RomCode design,FPGA prototype verification was performed based on Palladium and Haps.Verification results show that the RomCode design functions normally and runs stably,improves the success rate of chip tape out,accelerates the progress of software development,and effectively supports the functional verification of other SoC modules.

关 键 词：SOC芯片 多核处理器 RomCode FPGA原型验证 

分 类 号：TN401[电子电信—微电子学与固体电子学]