基于JESD204B的信号采样系统设计  

Design of Signal Sampling System Based on JESD204B

作　　者：赵鑫 赵赟 ZHAO Xin;ZHAO Yun(The 723 Institute of CSSC,Yangzhou 225101,China)

机构地区：[1]中国船舶集团有限公司第七二三研究所,江苏扬州225101

出　　处：《舰船电子对抗》2023年第5期117-120,共4页Shipboard Electronic Countermeasure

摘　　要：提出了一种基于JESD204B的信号采样系统设计方案,介绍了同源时钟分发板卡以及多个模数转换器(ADC)+多个现场可编程门阵列(FPGA)的板卡架构设计,针对影响ADC同步和链路稳定的因素,提出了多ADC同步和链路最小确定性延迟实现方法。结果表明所有链路在反复上电的时候工作稳定可靠,能够实现多ADC同步和链路最小确定性延迟,具有较高的实际应用价值。This paper puts forward a design scheme of signal sampling system based on JESD204B,introduces the homologous clock distribution board and multiple analog to digital converters(ADCs)+multiple field programmable gate arrays(FPGAs)board architecture design,according to the factors affecting ADC synchronization and link stability,presents the implementation method based on multi-ADC synchronization and link minimum deterministic delay.Results show that all links work stably and reliably during repeated power-ups,and can achieve multi-ADC synchronization and link minimum deterministic delay,meanwhile has high practical application value.

关 键 词：采样系统 最小确定性延迟 模数转换同步 JESD204B 

分 类 号：TN911.7[电子电信—通信与信息系统]