基于7 nm NPU预布局的布图优化设计  

Floorplan optimization design of pre-placement based on 7 nm NPU

作　　者：陈力颖[1,2] 高祥 李勇 徐微[1,2] CHEN Liying;GAO Xiang;LI Yong;XU Wei(School of Electronics and Information Engineering,Tiangong University,Tianjin 300387,China;Tianjin Key Laboratory of Optoelectronic Detection Technology and System,Tiangong University,Tianjin 300387,China;Taizhou National Crystal Technology Co.,Ltd.,Taizhou 318014,Zhejiang Province,China)

机构地区：[1]天津工业大学电子与信息工程学院,天津300387 [2]天津工业大学天津市光电检测技术与系统重点实验室,天津300387 [3]台州国晶智芯科技有限公司,浙江台州318014

出　　处：《天津工业大学学报》2023年第5期75-80,共6页Journal of Tiangong University

基　　金：天津市科技计划资助项目(18ZXCLGX0090);天津市自然科学基金资助项目(18JCYBJC85400)。

摘　　要：为了解决7 nm布图设计中直通寄存器在自动布局时不能均匀分布且高宽比相差较大、纵向绕线较多的问题,提出在布图阶段提前布局直通寄存器,并将宏单元放置在模块上下两端以避开直通寄存器密集位置的优化方法;并针对7 nm工艺对宏单元位置的约束,通过工具命令语言(TCL)脚本修复宏单元在布图阶段引起的违例。结果表明:相较于摆放在四周的布图规划,优化后的布图规划中建立时间最差负违例(WNS)减少0.131 ns,负违例总和(TNS)下降约80%,纵向拥塞从9.23%降至0.98%,功耗下降约500 mW;优化布图后执行TCL脚本,宏单元引起的违例下降了288条,相较人工修复节约了90%以上的时间。In order to solve the problems of uneven distribution of through registers in the automatic layout,large aspect ratio difference and more longitudinal winding in the 7 nm floorplan design,an optimization method is proposed to lay out the through registers in advance during the floorplan stage and place marco cells at the upper and lower ends of module to avoid the dense locations of through registers.To address the constraints of the 7 nm process on the position of macro cells,a tool command language(TCL)script is used to fix violations caused by macro cells during the floorplan stage.The results show that compared to the floorplan placed around it,the optimized floorplan reduces the worst negative violation(WNS)of the establishment time by 0.131 ns,the total negative violation(TNS)by about 80%,vertical congestion from 9.23%to 0.98%,and power consumption by about 500 mW;after optimizing the floorplan and executing the TCL script,the number of violations caused by macro cell decreased by 288,saving more than 90%of the time compared to manual repair.

关 键 词：直通寄存器 宏单元 布图规划 拥塞 7 nm 

分 类 号：TN47[电子电信—微电子学与固体电子学]