一种基于FPGA的万兆以太网MAC层设计与实现  

Design and implementation of a 10 Gigabit Ethernet MAC layer based on FPGA

作　　者：安超群 李飞 An Chaoqun;Li Fei(Guangdong Vocational College of Mechanical and Electrical Technology,Guangzhou 510515,China;Guangzhou Haige Communications Industry Group Co.,Ltd.,Guangzhou 510663,China)

机构地区：[1]广东机电职业技术学院,广东广州510515 [2]广州海格通信集团股份有限公司,广东广州510663

出　　处：《无线互联科技》2023年第18期165-168,共4页Wireless Internet Technology

摘　　要：针对基于软件设计的万兆以太网MAC层无法满足高速数据实时传输的发展要求,文章提出了一种基于FPGA硬件平台的万兆以太网MAC层协议的设计与实现方案。该设计方案主要利用FPGA的并行处理能力,通过Verilog硬件描述语言完成万兆以太网MAC层数据实时处理的硬件设计,实现大带宽、低延时和高可靠性的万兆以太网MAC层的数据收发功能。试验验证表明:该设计方案实现了万兆以太网高速率的数据传输,具有低延时、高性能、高可靠性与简易性等优点。In response to the software based design of the 10 Gigabit Ethernet MAC layer being unable to meet the development requirements of high-speed real-time data transmission,a design and implementation scheme of the 10 Gigabit Ethernet MAC layer protocol based on FPGA hardware platform is proposed.This design scheme mainly uses the parallel processing ability of FPGA to complete the hardware design of real-time data processing of 10 Gigabit Ethernet MAC layer through Verilog hardware description language,and realize the data receiving and transmitting function of 10 Gigabit Ethernet MAC layer with large bandwidth,low delay and high reliability.Experimental verification shows that this design scheme achieves high-speed data transmission over 10 Gigabit Ethernet,excluding protocol overhead.It has the advantages of high performance,high reliability and simplicity.

关 键 词：万兆以太网 MAC控制器 并行CRC校验 并行数据处理 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]