扫描位移过程中低功耗测试的设计与实现  

Design and Implementation of Low Power Consumption Testing During Scan Shift

作　　者：李尤鹏 纪元法[1,2,3] 肖有军 雷鹏 Li Youpengg;Ji Yuanfa;Xiao Youjun;Lei Peng(School of Information and Communication,Guilin University of Electronic Technology,Guilin 541004,China;Guangxi Key Laboratory of Precision Navigation Technology and Application,Guilin University of Electronic Technology,Guilin 541004,China;National&Local Joint Engineering Research Center of Satellite Navigation Positioning and Location Service,Guilin 541004,China;Global Unichip Corp(Nanjing),Nanjing 210018,China)

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林5541004 [2]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林5541004 [3]卫星导航定位与位置服务国家地方联合工程研究中心,广西桂林541004 [4]创意电子(南京)有限公司,南京210018

出　　处：《半导体技术》2023年第11期1012-1019,共8页Semiconductor Technology

基　　金：国家自然科学基金资助项目(62061010,62161007);广西科技厅项目(桂科AA20302022,桂科AB21196041,桂科AB22035074,桂科AD22080061);广西八桂学者项目;广西高校中青年教师科研基础能力提升项目(2022KY0181);桂林市科技项目(20210222-1);桂林电子科技大学研究生创新项目;“认知无线电与信息处理”教育部重点实验室2022年主任基金资助项目。

摘　　要：针对扫描位移功耗过高带来的生产成本增加、良率降低的问题,提出采用时钟相位调整技术和逻辑阻隔技术相组合的方式来降低测试功耗。利用布局布线之后的时钟偏差和物理位置等信息对时钟相位进行调整,从而降低峰值功耗;通过寄存器输出端的扇出数量来决定阻隔逻辑电路插入点,从而降低平均功耗。将该方案应用于实际项目中,从面积、覆盖率、功耗角度分析了时钟相位调整技术和逻辑阻隔技术的特点。结果表明,在面积和覆盖率影响较小的情况下,采用两种技术组合后扫描位移的峰值功耗降低了73.24%,平均功耗降低了6.78%。该方案具有良好的实用性,可为大规模集成电路低功耗可测性设计提供参考。To address the issue of the increased production cost and decreased yield caused by high power consumption in scan shift,a combination of clock delay adjacent technology and logic isolation technology was proposed to reduce the test power consumption.The clock phase was adjusted by using the clock skew and physical location information after placement and routing to reduce the peak power consumption.The fan-out number of the output end of the register determined the insertion point of the isolation logic circuit,thus reducing the average power consumption.The proposed approach was implemented in a practical project,and the characteristics of clock delay adjacent technology and logic isolation technology were analyzed in terms of area,coverage and power consumption.The results demonstrate a 73.24%reduction in peak power consumption and a 6.78%reduction in average power consumption for scan shift with minor impact on area and coverage after combining these two technologies.The proposed approach exhibits good practicality and can provide references for low power consumption testability design of large-scale integrated circuits.

关 键 词：扫描测试 低功耗测试 位移功耗 时钟相位调整 阻隔逻辑电路 

分 类 号：TN791[电子电信—电路与系统]