高精度SAR ADC电容阵列设计及校准算法  

Design and Calibration Algorithm of High-Precision SAR ADC Capacitor Array

作　　者：金鹏展 丁晟 黄玮[2] 朱樟明[3] 居水荣[1,2] Jin Pengzhan;Ding Sheng;Huang Wei;Zhu Zhangming;Ju Shuirong(School of Internet of Things Engineering,Jiangnan University,Wuxi 214122,China;Department of Microelectronics,Jiangsu Vocational Technical College of Information Technology,Wuxi 214153,China;School of Integrated Circuits,Xidian University,Xi'an 710071,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]江苏信息职业技术学院微电子学院,江苏无锡214153 [3]西安电子科技大学集成电路学院,西安710071

出　　处：《半导体技术》2023年第11期1020-1029,共10页Semiconductor Technology

基　　金：江苏省高等学校自然科学研究项目(19KJB510027);江苏省“333工程”科研资助项目计划(BRA2020318);常州大学应用技术学院现代职教体系专本贯通教育教学改革研究课题(22ZBGT02)。

摘　　要：在高精度逐次逼近寄存器模数转换器(SAR ADC)中,电容阵列是SAR ADC的核心之一。电容阵列中的电容失配问题是导致转换精度降低的一个重要原因。为了尽可能改善这一问题,设计了一种6+6+6分段电容阵列,并且基于这种阵列设计了权重迭代算法的前台数字校准。该方法不需要额外的电容阵列,利用自身的电容阵列与比较器量化出电容失配,计算出每一位输出码的权重校准系数,用来对正常量化出的输出码进行编码,实现校准功能。仿真结果表明,引入电容失配的18 bit SAR ADC经过该算法校准后,信噪比(SNR)从77.6 dB提升到107.6 dB,无杂散动态范围(SFDR)从89.8 dB提升到125.6 dB,有效位数(ENOB)从12.54 bit提升到17.54 bit。在SMIC 0.18μm工艺下,该校准算法对高精度SAR ADC的动态性能具有较大提升。In the high-precision successive approximation register analog-to-digital converter(SAR ADC),the capacitor array is one of the cores of the SAR ADC.The capacitance mismatch problem in the capacitor array is an important reason for the reduction of conversion accuracy.In order to improve this problem as much as possible,a 6+6+6 segmented capacitor array was designed,and a foreground digital calibration of the weight iteration algorithm based on this array was designed.This method does not require additional capacitor arrays,and uses its own capacitor array and comparator to quantify the capacitance mismatch,and calculates the weight calibration coefficients of each bit output code,which are used to encode the normally quantized output code to realize the calibration function.The simulation results show that the signal-to-noise ratio(SNR)of the 18 bit SAR ADC with capacitance mismatch calibrated by the algorithm is increased from 77.6 dB to 107.6 dB,the spurious-free dynamic range(SFDR)is increased from 89.8 dB to 125.6 dB,and the effective number of bits(ENOB)is increased from 12.54 bit to 17.54 bit.Under the SMIC 0.18μm process,the calibration algorithm greatly improves the dynamic performances of the high-precision SAR ADC.

关 键 词：逐次逼近寄存器模数转换器(SAR ADC) 电容失配 电容阵列 校准 有效位数(ENOB) 信噪比(SNR) 

分 类 号：TN792[电子电信—电路与系统] TN432