Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design  

作　　者：Devenderpal Singh Shalini Chaudhary Basudha Dewan Menka Yadav 

机构地区：[1]Department of Electronics and Communication Engineering,Malaviya National Institute of Technology,Jaipur,Rajasthan-302017,India

出　　处：《Journal of Semiconductors》2023年第11期89-100,共12页半导体学报（英文版）

摘　　要：This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

关 键 词：short channel effects(SCEs) junctionless FinFET analog and RF parameters SIGE 

分 类 号：TN386[电子电信—物理电子学]