晶上系统电源分配网络建模及IR-drop研究  

Modeling and IR-drop Analysis of Power Distribution Network for Waferscale Processors

作　　者：王家怡 朱熙铖 顾林 王梦雅 WANG Jiayi;ZHU Xicheng;GU Lin;WANG Mengya(School of Electronic&Information Engineering,Nanjing University of Information Science&Technology,Nanjing,210044,CHN;The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi,Jiangsu,214035,CHN)

机构地区：[1]南京信息工程大学电子与信息工程学院,南京210044 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《固体电子学研究与进展》2023年第5期401-407,共7页Research & Progress of SSE

基　　金：国家重点研发计划项目(2022YFB4401503);中国博士后科学基金项目(2022M712975)。

摘　　要：为预测和评估晶上系统电性能,提出了一种结合电磁和分析模拟的晶上系统电源分配网络(PDN)建模方法。该方法将PDN结构划分为单独组件,用电磁工具和公式计算提取无源电阻、电感、电容参数后,按组件位置组装成等效电路模型。通过与三维全波仿真自阻抗曲线比较对模型进行了验证,并基于模型,用ADS研究了模组位置排布、垂直互连密度、芯片功耗及去耦电容对电压降(IR-drop)的影响。结果表明:模型自阻抗曲线与三维全波仿真基本吻合;在一定范围内,合理排布模组位置、增加垂直互连密度、减少芯片功耗、使用较大去耦电容能降低IR-drop,为晶上系统设计和制造提供了参考。To predict and evaluate the electrical performance of waferscale processors,a power distribution network(PDN)modeling method which combines electromagnetic and analytical simulation was proposed.In this method,the PDN structure was divided into separated components.The passive resistance,inductance and capacitance(RLC)parameters were extracted and calculated through electromagnetic tools and formula.Then they were assembled into equivalent circuit model.The model was verified by comparing with 3D full wave model in self-impedance curve.Based on the model,the impacts of module placement,vertical interconnection density,chip power consumption and decoupling capacitance on voltage drop(IR-drop)were investigated by ADS.The results show that the self-impedance curve of model is basically consistent with 3D full wave model.Within a certain range,reasonable module placement,increased vertical interconnect density,reduced chip power consumption and the use of larger decoupling capacitors can reduce IR-drop,which provides a reference for design and manufacture of waferscale processors.

关 键 词：晶上系统 电源分配网络 电磁和分析模拟 等效电路模型 电压降 

分 类 号：TN405[电子电信—微电子学与固体电子学]