A Scalable Interconnection Scheme in Many-Core Systems  

作　　者：Allam Abumwais Mujahed Eleyat 

机构地区：[1]Computer Systems Engineering,Arab American University,Jenin,240,Palestine

出　　处：《Computers, Materials & Continua》2023年第10期615-632,共18页计算机、材料和连续体（英文）

摘　　要：Recent architectures of multi-core systems may have a relatively large number of cores that typically ranges from tens to hundreds;therefore called many-core systems.Such systems require an efficient interconnection network that tries to address two major problems.First,the overhead of power and area cost and its effect on scalability.Second,high access latency is caused by multiple cores’simultaneous accesses of the same shared module.This paper presents an interconnection scheme called N-conjugate Shuffle Clusters(NCSC)based on multi-core multicluster architecture to reduce the overhead of the just mentioned problems.NCSC eliminated the need for router devices and their complexity and hence reduced the power and area costs.It also resigned and distributed the shared caches across the interconnection network to increase the ability for simultaneous access and hence reduce the access latency.For intra-cluster communication,Multi-port Content Addressable Memory(MPCAM)is used.The experimental results using four clusters and four cores each indicated that the average access latency for a write process is 1.14785±0.04532 ns which is nearly equal to the latency of a write operation in MPCAM.Moreover,it was demonstrated that the average read latency within a cluster is 1.26226±0.090591 ns and around 1.92738±0.139588 ns for read access between cores from different clusters.

关 键 词：MANY-CORE MULTI-CORE N-conjugate shuffle multi-port content addressable memory interconnection network 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]