MRC:谐振时钟数字集成全局功耗优化方法  

MRC:global power optimization method of resonant clock for digital integration

作　　者：贾柯 杨梁 王剑[1,2,3] JIA Ke;YANG Liang;WANG Jian(State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;University of Chinese Academy of Sciences,Beijing 100049;Loongson Technology Corporation Limited,Beijing 100190)

机构地区：[1]计算机体系结构国家重点实验室(中国科学院计算技术研究所),北京100190 [2]中国科学院计算技术研究所,北京100190 [3]中国科学院大学,北京100049 [4]龙芯中科技术股份有限公司,北京100190

出　　处：《高技术通讯》2023年第11期1146-1159,共14页Chinese High Technology Letters

基　　金：中国科学院战略性先导科技专项(XDC05020100)资助项目。

摘　　要：本研究针对谐振时钟网络在集成电路设计中的数字化实现,提出了一种全局时钟功耗优化(MRC)方法,简化了谐振时钟网络在数字化设计中的集成过程。当前,依赖传统仿真工具构建谐振网络的仿真周期较长,且现有谐振电路模型无法满足快速设计与数字化建库要求。本文根据谐振电路三段式电路状态提出一种折线化模型降阶方法,可快速实现对当前各类谐振电路波形的准确刻画;本文同时基于此模型给出全局功耗优化目标函数,为电路选型提供指导。与12 nm Fin-FET工艺下实际电路的Spice后仿结果进行比较,本文模型精确度在90%以上,可以准确模拟实际功耗变化趋势,基于Matlab实现的优化方案相比Spice仿真提速10^(5)倍。Aiming at the digital implementation of resonant clock network in the integrated circuit design,this paper proposes a modeling and optimization method of resonant clock circuits(MRC),which simplifies the integration process of resonant clock networks.At present,traditional simulation tools for building resonant circuit models is time consuming,and the existing resonant circuit models cannot meet the requirements of rapid implementation and digital library construction.According to the three-stage circuit state of the resonant designs,the polyline reduction model in this paper can obtain the current waveforms of various resonant circuits quickly and accurately.An optimization objective function of global power consumption is also given based on this model,providing a theoretical basis for the selection of circuit parameters.The post-Spice simulation results based on 12 nm Fin-FET technology show that the model accuracy is more than 90%and can accurately fit the actual power consumption trend.Matlab-based implementation of the proposed model can achieve 10^(5) times speedup compared with Spice-based simulation.

关 键 词：谐振时钟 低功耗设计 功耗模型 设计方法学 大规模集成电路时钟设计 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]