数字锁相环频率跟踪控制方法的优化设计  

Optimal Design of Digital Phase Locked Loop Frequency Tracking Control Method

作　　者：刘宁庄[1] 张文婧 许龙[2] 龙路阳 LIU Ning-zhuang;ZHANG Wen-jing;XU Long;LONG Lu-yang(Xi'an University of Science and Technology,Xi'an 710054,China;不详)

机构地区：[1]西安科技大学,电气与控制工程学院,陕西西安710054 [2]中国计量大学,物理学院,浙江杭州310018

出　　处：《电力电子技术》2023年第11期19-22,共4页Power Electronics

基　　金：国家自然科学基金(12074354)。

摘　　要：针对超声波电源系统中换能器发热、磨损以及负载变化等原因引起谐振频率漂移的问题,提出了一种优化的全数字锁相环(PLL)频率跟踪控制方法。该方法采用自采样比例积分微分(PID)控制,基于数字鉴相器输出的相位误差大小调节数字序列滤波器的计数值,在保证系统稳定运行的同时提高了系统的响应速度。还可以作为一个功能模块来构成片上系统(SoC),提升系统运行可靠性的同时减少逻辑资源利用率,最后通过仿真和实验验证该理论的正确性。An optimized all digital phase locked loop(PLL)frequency tracking control method is proposed to solve the problem of resonant frequency drift caused by heat,wear and load changes of transducers in the ultra generated wave power supply system.This method uses self sampling proportional integral differential(PID)control to adjust the cou-nt value of the digital sequence filter based on the phase error output from the digital phase discriminator,ensuring stable operation of the system while improving the response speed of the system.It can also be used as a functional module to form a system on chip(SoC),improving system operational reliability while reducing logical resource utili-zation.Finally,the correctness of the theory is verified through simulation and experiments.

关 键 词：超声波电源 锁相环 比例积分微分 

分 类 号：TN86[电子电信—信息与通信工程]