一种高效FPGA模块验证模型  

An Efficient FPGA Module Verification Model

作　　者：毛茏玮 黄博 李勇 MAO Longwei;HUANG Bo;LI Yong(Chengdu Guoxinan Information Industry Base Co.,Ltd.,Chengdu Sichuan 610041,China)

机构地区：[1]成都国信安信息产业基地有限公司,四川成都610041

出　　处：《通信技术》2023年第11期1316-1323,共8页Communications Technology

摘　　要：目前现场可编程门阵列(Field-Programmable Gate Array,FPGA)模块验证存在复杂度高、规模大、耗时成本高等问题。针对上述问题探讨了一种高效的FPGA模块验证模型,该模型采用流水线设计,包括SVS、ALV、DLV、BLV、DM 5个阶段,对每个流程详细阐述了验证方法、测试类型及合理化步骤,其中,对模型的高效性进行了充分讨论。此外,采用功能仿真与实物测试的方法对优化手段进行了验证。最后,通过大量样本数据对高效模型万行耗时下降比α、万行缺陷率β进行汇总分析。从实验数据可知,所提验证模型结构完备、可靠性高、针对性强、验证效率高。At present,FPGA(Field-Programmable Gate Array)module verification has problems such as high complexity,large scale,and high time-consuming,etc.In response to these problems,this paper proposes an efficient FPGA module verification model.The model adopts a flow line design that includes five phases:SVS,ALV,DLV,BLV,and DM,each of which elaborates the specific verification methods,test types,and rationalization steps.Among them,the efficiency of the model is discussed in detail.In addition,functional simulation and physical testing methods are employed to verify the optimization means.Finally,a large amount of sample data is used to summarize and analyze the high-efficiency model time-consuming reduction ratioαof 10000 lines and defect rateβof 10000 lines.It is concluded from the experimental data that the proposed verification model has complete structure,high reliability,strong pertinence,and high verification efficiency.

关 键 词：FPGA软件 验证模型 高效模型万行耗时下降比 万行缺陷率 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]