一种基于有限脉冲响应滤波器的时钟倍频器设计  

A Design of Clock Frequency Multiplication Circuit Based on Finite Impulse Response Filter

作　　者：曾兆权 旭阳欣 马丁·马林森 张岭 张宁[1] ZENG Zhao-quan;HSU Yong-sheng;MALLINSON Martin;ZHANG Ling;ZHANG Ning(College of Mechanical and Electrical Engineering,Shihezi University,Shihezi,Xinjiang 832000,China;Yssheong Technology Inc.,Suwon 16203,Korea;Siliconintevention Inc.,Kelowna,BC V1W 1A4,Canada)

机构地区：[1]石河子大学机械电气工程学院,新疆石河子832000 [2]亿升科技有限公司,韩国水原16203 [3]硅谷接入有限公司,加拿大基洛纳V1W 1A4

出　　处：《电子学报》2023年第10期2791-2800,共10页Acta Electronica Sinica

基　　金：石河子大学国际科技合作推进计划项目(No.GJHZ202106)。

摘　　要：本文提出了一种基于有限脉冲响应(Finite Impulse Response,FIR)滤波器的时钟倍频与抖动消除电路.相比传统时钟倍频器所采用的锁相环(Phase Locked Loop,PLL)或延迟锁定环(Delay-Locked Loop,DLL)技术,本文所设计的倍频电路通过FIR滤波器原理来产生高精度的时钟相位,并利用新型过零检测电路来产生输出时钟脉冲,在明显降低时钟抖动的同时还实现了倍频器的快速锁定,且在功耗及面积成本上也更为经济.本设计采用SMIC 0.18μm CMOS工艺实现后,设置输入时钟频率为32 MHz时,在锁定时间小于1.5个时钟周期的情况下实现了5倍频输出,输入时钟抖动也从43.6 ps RMS降低至24.6 ps RMS,由此验证了设计的合理性和实用性.This paper presents a clock multiplication and jitter reduction circuit based on finite impulse response(FIR)filters.Compared with phase-locked loop(PLL)or delay-locked loop(DLL)techniques used in conventional clock multiplier,the proposed clock multiplier generates a high-precision clock phase based on the working principle of FIR filter while reducing the clock frequency jitter.A new zero-crossing detection circuit is also designed to generate output clock pulses.The proposed clock multiplier can achieve fast lock-in time,as well as low power consumption and area cost.This design is implemented in SMIC 0.18 um CMOS process,the input clock frequency is 32 MHz,the output is multiplied by 5 when the lock-in time is less than 1.5 clock cycles,and the input clock jitter is reduced from 43.6 ps RMS to 24.6 ps RMS.

关 键 词：时钟 倍频器 有限脉冲响应 过零检测 抖动 

分 类 号：TN771[电子电信—电路与系统]