一种抗噪声折叠宽范围低杂散小数分频锁相环  

An anti-noise folding wide range low spur fractional-N PLL

作　　者：蔡剑茹 尹勇生[1,2] 滕海林 杨文杰 孟煦 CAI Jianru;YIN Yongsheng;TENG Hailin;YANG Wenjie;MENG Xu(Institute of VLSI Design,Hefei University of Technology,Hefei 230601,China;IC Design Web-cooperation Research Center of Ministry of Education,Hefei University of Technology,Hefei 230601,China)

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230601 [2]合肥工业大学教育部IC设计网上合作研究中心,安徽合肥230601

出　　处：《合肥工业大学学报（自然科学版）》2023年第12期1666-1670,1693,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61704043)。

摘　　要：由于电荷泵的电流失配,小数分频锁相环反馈路径上经整形的量化噪声会被折叠回低频偏处,恶化带内相位噪声的性能。文章提出一种自适应的抗噪声折叠技术,根据工作频率产生合适脉宽的电流以线性化环路,在全频带内避免噪声折叠的同时不恶化参考杂散性能;设计基于TSMC 130 nm CMOS工艺,锁相环覆盖的输出频率范围为0.6~2.7 GHz。仿真结果显示:当输出频率为2.0 GHz时,环路功耗为16 mW,积分抖动为1.98 ps,品质因数为-222 dB;在电荷泵中引入8%的失配后,提出的技术改善带内相位噪声达到7 dB。With the current mismatch in charge pump,quantization noise on the feedback path of a fractional-N phase locked loop(PLL)might be folded back to low frequency offset,thus deteriorating the in-band phase noise performance.This paper proposed an adaptive anti-noise folding technique,which linearized the loop with pulsed current that has proper width according to the operating frequency.Noise folding could be avoided in overall output frequency range without decreasing the reference spur performance.The design was made with TSMC 130 nm CMOS technology,and the PLL covered an output frequency ranging from 0.6-2.7 GHz.The simulation results showed that the loop consumed 16 mW when generating an output frequency of 2.0 GHz,and the integrated jitter was 1.98 ps,corresponding to an FOM of-222 dB.With 8% mismatch in charge pump,the proposed technique improved the in-band phase noise by 7 dB.

关 键 词：小数分频锁相环 噪声折叠 带内相位噪声 参考杂散 低抖动 

分 类 号：TN911.8[电子电信—通信与信息系统]