基于JESD204B协议的智能信号处理SoC中自适应缓冲结构  

Adaptive Buffer Structure in Intelligent Signal Processing SoC Based on JESD204B Protocol

作　　者：魏赛 王鹏[1] 吴剑潇 陆斌 邢志昂 Wei Sai;Wang Peng;Wu Jianxiao;Lu Bin;Xing Zhiang(School of Computer Engineering and Science,Shanghai University,Shanghai 200444,China)

机构地区：[1]上海大学计算机工程与科学学院,上海200444

出　　处：《半导体技术》2023年第12期1115-1120,共6页Semiconductor Technology

摘　　要：JESD204B(简称204B)是智能信号处理系统级芯片(SoC)中连接高速模数/数模(AD/DA)转换的重要接口,将SoC系统结构与204B标准要求进行集成设计时,自适应缓冲结构(ABS)可弥补204B协议对数据传输缺乏流量控制的缺陷,并通过设置自适应缓冲与流控机制,保证数据传输的可靠性。经过现场可编程门阵列(FPGA)验证,SoC在204B接口可以达到4×12.5 Gbit/s的数据传输带宽,证明设计的204B接口方案在智能信号处理SoC中的可行性和有效性,满足智能信号处理SoC对于数据接口的要求。该设计方案的实现对无流量控制数据传输协议与SoC体系结构的集成有借鉴意义。JESD204B(abbreviated as 204B)is an important interface for connecting high-speed analog-to-digital/digital-to-analog(AD/DA)conversion in intelligent signal processing system-on-chips(SoCs).When integrating SoC system structure with 204B standard requirements,adaptive buffer struc-ture(ABS)can compensate the imperfect of 204B protocol that lack of flow control for data transmission,and by setting up adaptive buffer and flow control mechanism,data transmission reliability can be guaranteed.Verified by field-programmable gate array(FPGA),the SoC can achieve a data transmission bandwidth of 4×12.5 Gbit/s at 204B interface,proving the feasibility and validity of the designed 204B interface scheme in the intelligent signal processing SoC,and meeting the requirements of the intelligent signal processing SoC for data interface.The implementation of the scheme is useful for integrating flowless control data transmission protocols with SoC structures.

关 键 词：系统级芯片(SoC) JESD204B 现场可编程门阵列(FPGA)验证 直接内存访问(DMA) 先进可扩展接口(AXI) 

分 类 号：TN492[电子电信—微电子学与固体电子学]