应用于∑-ΔADC调制器的高增益运算放大器  

A high gain operational amplifier applied to∑-ΔADC modulator

作　　者：杨小峰 雷城 YANG Xiaofeng;LEI Cheng(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;Xi’an Xingpan Electronic Technology Co.,Ltd,Xi’an 710075,China)

机构地区：[1]西安邮电大学电子工程院,陕西西安710121 [2]西安星磐电子科技有限公司,陕西西安710075

出　　处：《西安邮电大学学报》2023年第5期40-49,共10页Journal of Xi’an University of Posts and Telecommunications

基　　金：陕西省重点研发计划项目(2022GY-010)。

摘　　要：为了提高∑-Δ调制器中运算放大器(运放)的增益,提出了一种应用于∑-Δ调制器的高增益运放设计方案。所设计的运放使用增益提升型结构,主要包含两个辅助放大器和一个主放大器,这3个放大器皆为折叠共源共栅结构。采用在辅助放大器和主放大器的输出极点之间添加补偿电容的方法,以补偿总运放的频率特性,使其能够稳定工作。仿真结果表明,该放大器的增益为120.6 dB,相位裕度为62.3°,电源抑制比为185.9 dB,共模抑制比为179.1 dB。与其他高增益设计方法相比,所提设计方案可以有效地提升运放的增益。In order to improve the gain of the operational amplifier in the∑-Δmodulator,a high-gain operational amplifier design scheme for the∑-Δmodulator is proposed.The designed operational amplifier has a gain-boosting structure,and mainly includes two auxiliary amplifiers and a main amplifier.All the three amplifiers have folded cascode structures.A compensation capacitor is added between the output poles of the auxiliary op amp and the main op amp,to compensate for the frequency characteristics of the total op amp,to make it work stably.The simulation results show that the amplifier has a gain of 120.6 dB,a phase margin of 62.3°,a power supply rejection ratio(PSRR)of 185.9 dB,and a common mode rejection ratio(CMRR)of 179.1 dB.Compared with other high-gain design methods,the proposed scheme can effectively increase the gain of the operational amplifier.

关 键 词：∑-Δ调制器 运算放大器 增益提升结构 补偿电容 频率特性 

分 类 号：TN721.1[电子电信—电路与系统]