ESD防护仿真技术研究  

Research on System-level ESD Protection Simulation

作　　者：蒋云昊 陈奕鹏 朱信宇 高志良[2] 程千钉 周黎[2] 董树荣[1] Jiang Yunhao;Chen Yipeng;Zhu Xinyu

机构地区：[1]浙江大学信息与电子工程学院 [2]北京东方计量测试研究所

出　　处：《安全与电磁兼容》2024年第1期38-45,共8页Safety & EMC

基　　金：国家科技创新基金(2030-2021ZD0200401);北京东方计量测试研究所刘尚合院士专家工作站静电研究基金课题(BOIMTLSHJD20221003)。

摘　　要：静电放电(ESD)一直是电子产品的重大威胁,严重的还会造成芯片失效。在设计阶段需对芯片受ESD冲击后的耦合情况进行预测评估,并为芯片设计有效的ESD防护,实现系统级高效ESD设计(SEED)成为发展趋势。文章研究了瞬态抑制二极管(TVS)对静电的响应情况,并将TVS分为回滞型与非回滞型,分别建立了SPICE模型。提出了一种新的ESD发生器电路模型和全波模型,所得电流波形与实测数据吻合较好。两种模型的电流特征值与IEC 61000-4-2:2008要求的偏差较小。为复现完整的系统级ESD测试环境提供了支持,也为探索芯片在系统级ESD测试下的行为模式打下基础。Electrostatic discharge(ESD)has always posed a significant threat to electronic components and products,often resulting in severe chip failures.Predicting and evaluating the complex effects of ESD on electronic devices and their coupling during the chip design phase has become crucial in implementing effective ESD protection at the chip level.This trend has led to System-level Efficient ESD Design(SEED)as a development approach.For SEED at the board level,it primarily involves modeling the ESD generator and transient voltage suppressor(TVS)devices for general protection.This paper investigates the response of TVS to electrostatic discharges and establishes SPICE models for TVS,categorizing them into snapback and non-snapback types.Additionally,a new ESD generator circuit model and full-wave model are proposed,demonstrating good agreement with measured data in terms of current waveforms.The current characteristic values of both models exhibit little deviations from the IEC 61000-4-2:2008.This work provides support for replicating a comprehensive system-level ESD testing environment and lays the groundwork for exploring the behavioral patterns of chips under system-level ESD testing.

关 键 词：静电放电 芯片失效 系统级ESD设计 瞬态抑制二极管 静电枪 

分 类 号：TN03[电子电信—物理电子学] O441.1[理学—电磁学]