基于CEVA-XC4500 DSP平台5G-LDPC码编码实现  

Encoding Implementation of 5G-LDPC Codes on CEVA-XC4500 DSP Platform

作　　者：吴思远 陈成 姜明 徐安来 WU Siyuan;CHEN Cheng;JIANG Ming;XU Anlai(School of Information Science and Engineering,Southeast University,Nanjing 214135,China)

机构地区：[1]东南大学信息科学与工程学院,江苏南京214135

出　　处：《无线电工程》2024年第2期457-462,共6页Radio Engineering

基　　金：国家重点研发计划资助(2020YFB1807205)。

摘　　要：低密度奇偶校验(Low-Density Parity-Check,LDPC)码是第五代移动通信技术(5th Generation Mobile Communication Technology,5G)系统采用的信道编码技术之一,用于业务信道高速数据传输,具有很强的抗干扰能力和纠错能力。5G-LDPC码编译码在嵌入式平台的实现是一个值得关注的研究方向。CEVA-XC4500数字信号处理(Digital Signal Processing,DSP)芯片具有极低功耗、高密度计算、集成了超长指令字(Very Long Instruction Word,VLIW)和单指令多数据(Single Instruction Multiple Data,SIMD)矢量功能的特点。针对CEVA-XC4500 DSP矢量汇编指令和内联指令集的特点,提出一系列针对5G-LDPC码编码的代码优化方法,使其满足5G-LDPC码编码工程应用指标要求。仿真结果表明,优化后的5G-LDPC码编码在CEVA-XC4500 DSP内核上表现良好,中长块编码吞吐率超过100 Mb/s、核心矩阵吞吐率超过1 Gb/s,最大吞吐率达到250 Mb/s、最大核心矩阵吞吐率达到1.6 Gb/s。如果CEVA-XC4500 DSP芯片的最大数据位宽将来能进一步增大,吞吐率可以做得更好。该5G-LDPC码编码的代码优化方法为其他信道编码在类似嵌入式平台的实现提供了参考。Low-Density Parity-Check(LDPC)code is one of the channel coding techniques used in 5th Generation Mobile Communication Technology(5G)system,which is widely used for high-speed transmission over data channel and has strong anti-interference and error correction capabilities.The implementation of 5G-LDPC encoding and decoding in embedded platforms is a research direction worthy of attention.CEVA-XC4500 Digital Signal Processing(DSP)chip has the characteristics of extremely low power consumption and high density computing,and integrates Very Long Instruction Word(VLIW)and Single Instruction Multiple Data(SIMD)vector functions.According to the characteristics of CEVA-XC4500 DSP vector assembly instructions and inline instruction sets,a series of program optimization methods for 5G-LDPC code coding are proposed to meet the requirements for engineering applications of 5G-LDPC codes.The simulation results show that the optimized 5G-LDPC code encoding performs well on the CEVA-XC4500 DSP core,with a medium to long block encoding throughput rate exceeding 100 Mb/s,a core matrix throughput rate exceeding 1 Gb/s,a maximum throughput rate of 250 Mb/s,and a maximum core matrix throughput rate of 1.6 Gb/s.If the maximum data bit width of the CEVA-XC4500 DSP chip can be further increased in the future,the throughput rate can be improved.In addition,the program optimization method for 5G-LDPC encoding also provides a valuable reference for other channel coding implementations on similar embedded platforms.

关 键 词：CEVA-XC4500 DSP 超长指令字 单指令多数据 5G-低密度奇偶校验码编码 矢量化 

分 类 号：TN911.22[电子电信—通信与信息系统]