CAN FD总线位定时模块的设计与验证  

Design and verification of CAN FD bit timing module

作　　者：肖懿琳 杨红姣[1,2] 谢亮[2] XIAO Yi-Lin;YANG Hong-jiao;XIE Liang(Xiangtan University,Microelectronics and System Integration Hunan Engineering Laboratory;Postgraduate Joint Training Base for Xiangtan University-Hunan Silicon Internet of Things Technology Co.,Ltd.)

机构地区：[1]湘潭大学-微光电与系统集成湖南省工程实验室 [2]湘潭大学-湖南芯力特电子科技有限公司研究生联合培养基地

出　　处：《中国集成电路》2023年第12期51-56,70,共7页China lntegrated Circuit

摘　　要：随着汽车电子设备的发展,传统CAN总线难以满足传输速度快且传送容量大的要求,而CAN FD总线能在兼容CAN的同时提供更快速的通信。CAN FD总线位定时模块在保障CAN FD总线的正常收发过程中发挥重要作用,同时也是CAN FD控制器的重要组成部分和设计难点之一。本文依据ISO11898-1:2015标准研究CAN FD位定时机制,提出一种CAN FD位定时模块设计思路。此模块使用Verilog硬件描述语言实现,采用QuartusⅡ和Modelsim联合仿真来对位速率产生、位速率切换和同步操作功能进行验证。验证结果表明此设计符合ISO11898-1标准规定,能完成FD帧的位时间产生和切换,证明设计思路的正确性和可行性。With the development of automotive electronic devices,traditional CAN buses are difficult to meet the requirements of fast transmission speed and large transmission capacity.However,the recently proposed CAN FD bus can provide faster communication while being compatible with CAN.The CAN FD bus bit timing module plays an important role in ensuring the normal transmission and reception process of the CAN FD bus,and is also an important component and design difficulty of the CAN FD controller.This article studies the CAN FD bit timing mechanism based on the ISO11898-1:2015 standard and proposes a design concept for the CAN FD bit timing module.This module is implemented using Verilog hardware description language and uses Quartus II and Modelsim joint simulation to verify the bit rate generation,bit rate switching,and synchronization operation functions.The verification results indicate that this design meets the requirements of ISO11898-1 standard and can generate and switch the bit time of FD frames,proving the correctness and feasibility of the design concept.

关 键 词：CAN FD总线 位定时 同步 位速率切换 

分 类 号：U463.6[机械工程—车辆工程]