一种高共模电压集成差分放大器的设计  

Design of a high common-mode voltage differential amplifier

作　　者：张鑫 魏海龙[1] 尤路[1] 陈蒙 ZHANG Xin;WEI Hailong;YOU Lu;CHEN Meng(Xi'an Microelectronics Technology Institute,Xi'an 710054,China)

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2024年第2期52-57,共6页Microelectronics & Computer

摘　　要：针对差分放大器芯片国产化的需求,基于兼容金属薄膜电阻40 V双极工艺,设计一款高共模抑制比(Common Mode Rejection Ratio,CMRR)、±120 V共模输入电压的集成差分放大器。文章介绍了高共模电压差分放大器的基本原理和结构组成,分析了差分放大器的设计难点,分别为共模抑制比、输入失调电流以及增益误差,采用片内集成金属薄膜电阻结合激光在线修调技术实现高共模抑制比、通过改进型的基极电流补偿结构降低了输入失调电流,减少输入失调电流对电路采样精度的影响,采用改进型达林顿管提高放大器的开环增益,降低放大器的增益误差。整体芯片尺寸为2.82 mm×2.02 mm,采用±15 V双电源供电,静态电流为1.36 mA。流片后的测试结果表明:差分放大器在正常供电时,共模抑制比达到85 dB,输入失调电流仅为84 pA,失调电流的补偿精度达到98.1%,增益误差为0.02%。In response to the demand for localization of differential amplifier chip,this paper introduces a±120 V common-mode input voltage integrated differential amplifier with high Common Mode Rejection Ratio(CMRR)based on the 40 V bipolar process with metal thin film resistors.The article covers the basic principles and structural components of differential amplifiers,and analyzes the difficulties in the design process of differential amplifiers,including common-mode rejection ratio,input offset current and gain error.The methods to improve the CMRR and lower input offset current are introduced which are the technologies of integrated metal thin-film resistors trimmed by laser cutting and the modified base current compensation configuration,and improved Darlington tube is used to increase the open-loop gain of the amplifier and reduce the gain nonlinearity of the amplifier.The overall chip size is 2.82 mm×2.02 mm,the dual power is±15 V,and the current consumption is 1.36 mA.Experimental results show that,at supply voltage of±15 V,the CMRR is 85 dB and the input offset current is only 84 pA with 98.4%compensation precision,and the gain error is 0.02%.

关 键 词：差分放大器 高共模抑制比 高共模输入电压 基极电流补偿结构 

分 类 号：TN431[电子电信—微电子学与固体电子学]