异步BiSS-C协议的FPGA解码  

FPGA decoding of asynchronous BiSS-C protocol

作　　者：陈佳文 刘晴晴[1] 邵春江[1] CHEN Jiawen;LIU Qingqing;SHAO Chunjiang(Beijing Aerospace Automatic Control Institute,Beijing 100854,China)

机构地区：[1]北京航天自动控制研究所,北京100854

出　　处：《微电子学与计算机》2024年第2期101-107,共7页Microelectronics & Computer

摘　　要：为了在BiSS-C协议的处理器设备(Master,MA)时钟和现场可编程门阵列(Field Programmable Gate Array,FPGA)时钟异步的情况下获得BiSS-C协议传输的数据,提出一种异步时钟下FPGA解码BiSS-C协议的实现方法。首先,在FPGA中对BiSS-C传输的编码器数据进行16倍采样,用状态机解码BiSS-C数据,并对数据进行循环冗余校验(Cyclic Redundancy Check,CRC)。其次,在ModelSim中对FPGA软件进行仿真,对状态机的功能、FPGA软件的数据判读能力进行验证。最后,搭建光栅编码器数据采集系统,对FPGA的解码效果进行验证。仿真结果和试验结果表明:在异步时钟下FPGA能正确解码BiSS-C协议传输数据,解码得到的编码器角度位置误差不大于0.1'',误码率低、解码精度高。In order to obtain the data transmitted by BiSS-C when the Master(MA)clock of BiSS-C protocol and the Field Programmable Gate Array(FPGA)clock are asynchronous,an implementation method of FPGA decoding BiSS-C protocol under asynchronous clock is proposed.First,the encoder data transmitted by BiSS-C are sampled 16 times in the FPGA,and the BiSS-C data are decoded by the state machine and Cyclic Redundancy Check(CRC)is performed on the data.Secondly,the FPGA software is simulated in ModelSim to verify the function of the state machine and the data interpretation ability of the FPGA software.Finally,the encoder data acquisition system is built to verify the decoding effect of FPGA.The simulation results and experimental results show that the FPGA can correctly decode the data transmitted by the BiSS-C protocol under the asynchronous clock.The decoded encoder angular position error is not greater than 0.1 arcseconds,with low bit error rate and high decoding accuracy.

关 键 词：BiSS-C协议 现场可编程门阵列(FPGA) 异步时钟 数据解码 编码器 

分 类 号：TN792[电子电信—电路与系统]