应用于红外大面阵数据传输的接口电路设计  

Interface Circuit Design for Infrared Large Array Data Transmission

作　　者：陈方清 CHEN Fang-qing(Yantai IRay Technology Co.,Ltd.,Yantai 264000,China)

机构地区：[1]烟台艾睿光电科技有限公司,山东烟台264000

出　　处：《红外》2024年第2期28-35,共8页Infrared

摘　　要：红外大面阵(2560×2048)数字读出电路对芯片数据接口有高速、低功耗、强驱动能力的需求。采用0.18μm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺设计了4∶1并串转换电路、电平转换电路以及采用预加重技术的低压差分信号(Low Voltage Differential Signal,LVDS)驱动器电路。并串转换电路采用双沿采样的树形结构降低时钟频率,电平转换电路采用正反馈结构提升速度,LVDS驱动电路采用可编程电流大小的预加重副通路对主通路进行高频分量补偿,以保证驱动能力和提升高速信号的完整性。接口的数据传输速率可达到1 Gbit/s。当负载电容为2 pF时,一个通道的功耗为15.8 mW@1 Gbit/s;当负载电容为8 pF且打开预加重时,一个通道的功耗为19 mW@1Gbit/s,输出电压摆幅为350 mV,输出共模电平为1.21 V,LVDS驱动电路的所有参数均满足标准协议。Infrared large-area array(2560×2048)digital readout circuits require high-speed,low-power consumption,and strong driving capabilities for chip data interfaces.Using 0.18 μm complementary metal oxide semiconductor(CMOS)process,a 4∶1 parallel-to-serial conversion circuit,a level translation circuit,and a low voltage differential signal(LVDS)driver circuit using pre-emphasis technology were designed.The parallel-to-serial conversion circuit adopts a double-edge sampling tree structure to reduce clock frequency,the level translation circuit adopts a positive feedback structure to improve the speed,and the LVDS driving circuit uses a pre-emphasis secondary path with programmable current to compensate for high-frequency components in the main path,ensuring driving capability and improving the integrity of high-speed signals.The data transmission rate of the interface can reach 1 Gbit/s,and when the load capacitance is 2 pF,the power consumption of one channel is 15.8 mW@1 Gbit/s;When the load capacitance is 8 pF,with pre-emphasis turned on,the power consumption of one channel is 19 mW@1 Gbit/s,the output voltage swing is 350 mV,and the output common-mode level is 1.21 V.All parameters of the LVDS drive circuit meet the standard protocol.

关 键 词：高速接口电路 并串转换 低压差分信号 预加重 

分 类 号：TN432[电子电信—微电子学与固体电子学]