基于FPGA的PAL图像数据解码与传输设计  

Design of PAL image data decoding and transmission based on FPGA

作　　者：赵清琳 任勇峰[1] 武旌阳 ZHAO Qinglin;REN Yongfeng;WU Jingyang(Key Laboratory of Instrumentation Science and Dynamic Measurement of Ministry of Education,National Key Laboratory of Electronic Measurement Technology,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学电子测试技术国家重点实验室仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《集成电路与嵌入式系统》2024年第3期94-98,共5页INTEGRATED CIRCUITS AND EMBEDDED SYSTEMS

摘　　要：为了满足地面监控设备将视频数据快速上传至存储设备的需求,解决图像传感器输出PAL制信号的模拟解码和数据传输的问题,设计了基于FPGA的PAL数据输入、网络接口输出的硬件模块。通过解码器将PAL模拟信号转换为并行数字信号,并在FPGA端将输入数据进行奇偶场数据缓存,通过乒乓操作实现隔行转逐行的视频输出。同时在FPGA内部采用调用MAC软核的方式在UDP协议上增加重传机制和异步FIFO,实现数据的网络传输。In order to meet the needs of the ground monitoring equipment to upload video data to the storage device quickly,solve the problem of analog decoding and data transmission of image sensor output PAL signal,this paper designs the PAL data input and network interface output hardware module based on FPGA.The PAL analog signal is converted into parallel digital signal by decoder,and the in-put data is cached by parity field data in FPGA,and the interlaced video output is realized by ping-pong operation.At the same time,in the way of calling MAC soft core inside FPGA,retransmission mechanism and asynchronous FIFO are added to UDP protocol to realize data network transmission.

关 键 词：FPGA 千兆以太网 PAL UDP FIFO 

分 类 号：TN914.3[电子电信—通信与信息系统]