改进的共享布尔逻辑进位选择加法器设计  

Design of an Improved Shared Boolean Logic Carry Select Adder

作　　者：吴盛林 WU Shenglin(School of Computer Science and Engineering,Anhui University of Science and Technology,Huainan 232001,China)

机构地区：[1]安徽理工大学计算机科学与工程学院,安徽淮南232001

出　　处：《现代信息科技》2024年第4期61-65,共5页Modern Information Technology

摘　　要：在当今高度数字化和计算密集型的环境下,设计出高速和低功耗的加法器,例如进位选择加法器(Carry Select Adder,CSLA)是至关重要的。基于此提出一种改进共享布尔逻辑进位选择加法器。与现有设计相比,该设计在牺牲部分功耗和速度的基础上,减少了晶体管数量。该设计采用TSMC65nm工艺在Cadence中实现了4位的设计。仿真结果显示,相对于Fast Adder Module-2(FAM2)进位选择加法器,该方案的晶体管数量、功耗和功耗延时积分别降低了8.91%、8.13%和6.02%。In today's highly digitized and computationally intensive environment,it is crucial to design high-speed and low-power adders,such as Carry Select Adders(CSLA).Based on this,an improved shared Boolean logic Carry Select Adder is proposed.Compared to existing designs,this design reduces the number of transistors on the basis of sacrificing some power consumption and speed.This design utilizes TSMC65 nm technology to achieve 4-bit design in Cadence.The simulation results show that compared to the Fast Adder Module-2(FAM2)Carry Select Adder,this scheme reduces the number of transistors,power consumption,and power consumption delay product by 8.91%,8.13%,and 6.02%,respectively.

关 键 词：进位选择加法器 晶体管数量 功耗 延迟 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构] TP391.9[自动化与计算机技术—计算机科学与技术]