一款基于45 nm SOI CMOS工艺的高功率二倍频器  

A high power frequency doubler basedon 45nm CMOS-SOI process

作　　者：陈奇超 叶乔霞 张超 王梓任 高海军[1] CHEN Qichao;YE Qiaoxia;ZHANG Chao;WANG Ziren;GAO Haijun(Key Laboratory for RF Circuits and Systems,Ministry of Education,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China)

机构地区：[1]杭州电子科技大学射频电路与系统教育部重点实验室,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2023年第5期14-20,29,共8页Journal of Hangzhou Dianzi University：Natural Sciences

基　　金：国家自然科学基金资助项目(61871161)。

摘　　要：基于45 nm SOI CMOS工艺,设计了一款输出频率为10.04 GHz~19.26 GHz的高功率二倍频器。该二倍频采用push-push结构,能够滤除奇次谐波,留下偶次谐波。为了提高倍频管二次谐波的功率,将MOS管偏置在C类。在二倍频器的输入端,采用二次谐波短路回路来提高倍频转换增益;同时,为了实现巴伦中心交流接地及平衡信号,在巴伦中心抽头处加入了一个电容。后仿真结果表明:在输入功率为0 dBm下,3 dB绝对带宽范围为10.04 GHz~19.26 GHz,相对带宽为62.9%。在带宽内基波抑制达到了27 dBc以上。最大转换增益为4.9 dBm。直流功耗峰值为26 mW。其最大功率附加效率为15.4%。芯片核心面积仅为0.264 mm^(2)。Based on a 45 nm SOI CMOS process,a high power frequency doubler with output frequency 10.04 GHz~19.26 GHz is designed.The frequency doubler adopts push-push structure,which can remove odd harmonics and leave even harmonics.In order to improve the power of the second harmonic of the transistor,the transistors are biased in class C.At the input of the frequency doubler,the second harmonic short circuit is used to improve the conversion gain.At the same time,in order to realize the AC grounding of the balun center and to balance different signals,a capacitor is added at the tap of the balun center.The simulation results show that the absolute bandwidth range of 3 dB is 10.04 GHz~19.26 GHz and the relative bandwidth is 62.9%when the input power is 0 dBm.Within 3dB bandwidth,the fundamental suppression reaches more than 27 dBc,the maximum conversion gain is 4.9 dBm,the peak DC power consumption is 26 mW,the maximum power added efficiency is 15.4%,and the core area of the chip is only 0.264 mm^(2).

关 键 词：SOI CMOS push-push倍频器 巴伦 二次谐波短路回路 高功率 

分 类 号：TN432[电子电信—微电子学与固体电子学]