基于阵列处理器的HEVC数据流图可重构实现  

RECONFIGURABLE IMPLEMENTATION OF HEVC DATA FLOW GRAPH BASED ON ARRAY PROCESSOR

作　　者：胡传瞻 蒋林 朱筠 谢晓燕 杨坤 崔馨月 Hu Chuanzhan;Jiang lin;Zhu Yun;Xie Xiaoyan;Yang Kun;Cui Xinyue(School of Computer,Xi’an University of Posts&Telecommunications,Xi’an 710121,Shaanxi,China;Laboratory of Integrated Circuit,Xi’an University of Science and Technology,Xi’an 710054,Shaanxi,China;School of Electronic Engineering,Xi’an University of Posts&Telecommunications,Xi’an 710121,Shaanxi,China)

机构地区：[1]西安邮电大学计算机学院,陕西西安710121 [2]西安科技大学集成电路实验室,陕西西安710054 [3]西安邮电大学电子工程学院,陕西西安710121

出　　处：《计算机应用与软件》2024年第3期240-245,257,共7页Computer Applications and Software

基　　金：国家自然科学基金项目(61772417,61834005,61802304,61602377)。

摘　　要：提出一种基于阵列处理器的HEVC算法数据流图可重构实现方法。基于动态重构机制完成不同的划分方式、算法间的灵活切换,采用深度优先贪婪对数据流图划分后子任务时域流水的并行方式对HEVC中典型编码算法的数据流图重新划分后设计合理映射方案,以Sobel算子值为重构依据在阵列处理器上进行帧内预测算法验证。实验结果表明,与块间流水方案实现相比加速比可达14.97,各算法资源利用率及计算速度均有提升,与帧内预测模式选择快速算法相比每个时钟周期可多处理7.1个像素。This paper presents a reconfigurable implementation method of HEVC algorithm data flow graph based on array processor.Based on the dynamic reconstruction mechanism,the flexible switching between different partition methods and algorithms was completed.The data flow graph of typical coding algorithms in HEVC was redivided by depth first greedy parallel mode of time-domain pipelining of sub tasks after data flow graph partition.After that,a reasonable mapping scheme was designed.The intra prediction algorithm was verified on array processor based on Sobel operator value.The experimental results show that compared with the inter block pipelining scheme,the speedup ratio can reach 14.97,and the resource utilization and computing speed of each algorithm are improved.Compared with the fast intra prediction mode selection algorithm,each clock cycle can process 7.1 more pixels.

关 键 词：数据流图 HEVC 深度优先贪婪 可重构阵列处理器 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]