一种用于锁相环的环形压控振荡器设计  

The invention relates to the design of a ring VCO for a phase-locked loop

作　　者：李娜 陆锋[1,2] 王星 张国贤 LI Na;LU Feng;WANG Xing;ZHANG Guo-xian(School of Internet of Things Engineering,Jiangnan University;The 58th Institute of China Electronics Technology Group Corporation)

机构地区：[1]江南大学物联网工程学院 [2]中国电子科技集团公司第五十八所

出　　处：《中国集成电路》2024年第3期36-39,49,共5页China lntegrated Circuit

摘　　要：本文基于SMIC 65nm标准CMOS工艺提出了一种用于锁相环的环形压控振荡器的电路设计。包括了环形振荡器和缓冲整形电路。该环形压控振荡器有四级延时单元,并且延时单元采用了Maneatis对称负载。该电路在Cadence Spectre进行了仿真。结果表明,在电源电压1.8V时,频率调整范围为0.277GHz~1.33GHz,具有良好的线性度。频偏为1MHz时的相位噪声为-92.46dBc/Hz@1MHz,有良好的噪声性能。缓冲整形电路将压控振荡器的输出波形转换为轨到轨电压,使占空比等于50%,并提高了驱动能力。振荡器的稳定频率分别为400/500MHz。In this paper,based on 65nm standard CMOS technology,a circuit design of ring VCO for phase-locked loop(PLL)is proposed.Includes a ring oscillator and a buffer shaping circuit.The ring VCO has a four-stage delay unit,and the delay unit adopts Maneatis symmetrical load.Simulation on Cadence Spectre.The results show that when the power supply voltage is 1.8V,the frequency adjustment range is 0.277~1.33GHz,with good linearity.When the frequency offset is 1MHz,the phase noise is-92.46dBc/Hz@1MHz,which has good noise performance.The buffer shaping circuit converts the output waveform of the VCO to rail to rail voltage,resulting in a duty ratio equal to 50%and improved drive capability.The oscillators are stabilized at 400/500MHz respectively.

关 键 词：环形压控振荡器 锁相环 延迟单元 比较器 

分 类 号：TN752[电子电信—电路与系统]