基于55 nm DICE结构的单粒子翻转效应模拟研究  

Three-dimensional numerical simulation of single event upset effect based on 55 nm DICE latch unit

作　　者：张幸 刘玉林 李刚 燕少安 肖永光 唐明华 Zhang Xing;Liu Yu-Lin;Li Gang;Yan Shao-An;Xiao Yong-Guang;Tang Ming-Hua(School of Materials Science and Engineering,Xiangtan University,Xiangtan 411105,China)

机构地区：[1]湘潭大学材料科学与工程学院,湘潭411105

出　　处：《物理学报》2024年第6期295-304,共10页Acta Physica Sinica

基　　金：国家自然科学基金(批准号:92164108,U23A20322,11835008);湖南省自然科学基金(批准号:2023JJ50009,2023JJ30599);辐射应用创新中心基金(批准号:KFZC2020020901)资助的课题。

摘　　要：单粒子翻转(single event upset,SEU)是器件在辐照空间中应用的关键难题,本文以55 nm加固锁存单元为研究载体,通过三维数值模拟方法,获得了重离子不同入射条件下的线性能量转移(linear energy transfer,LET)阈值和电压脉冲变化曲线,研究了双互锁存储单元(dual interlockded storage cell,DICE)的抗辐照性能和其在不同入射条件下的SEU效应.研究表明,低LET值的粒子以小倾斜角入射器件时,降低了器件间的总电荷收集量,使得主器件节点的电压峰值和电压脉宽最小,器件SEU敏感性最低;由于空穴与电子迁移率的差异,导致DICE锁存器中Nhit的入射角敏感性远大于Phit;合理调节晶体管间距可以削弱电荷共享效应,使得从器件总电荷收集量减小,仿真计算得到此工艺下晶体管间距不能小于1.2μm.相关仿真结果可为DICE锁存单元单粒子效应的物理机制研究和加固技术提供理论依据和数据支持,有助于加快存储器件在宇航领域的应用步伐.With the development of nanoscale circuit technology,the on-track error rate of digital circuit and the effect of single event upset have become more pronounced.The radiation resistance research on DICE SRAM or DICE flip-flop device has been carried out extensively,including 65 nm,90 nm,and 130 nm.However,the research on 55 nm DICE latch has not been reported.Using a three-dimensional device model of the 55 nm bulk silicon process established by the simulation tool TCAD,we verify the reinforcement performance of the DICE circuit,and clarify the effects of different incident conditions on DICE circuits.At the same time,we carry out a comparison of anti-SEU performance between NMOS transistor and PMOS transistor in the 55 nm process through comparative simulation experiments and quantitative analysis.The result shows that one of the important factors is the LET value which affects the generation rate of electron-hole pairs.A higher LET value will extend the upset recovery time of device and increase the peak of voltage.In addition,the difference in charge-sharing mechanism between transistors leads to the recovery time of PMOS higher than that of NMOS.As the angle of incidence increases,the charge-sharing mechanism between adjacent devices is enhanced,and electron-hole pairs ionized in sensitive regions increase.Due to the difference in charge mobility,the sensitivity of the angle of incidence of Nhit in DICE is much greater than that of Phit.Therefore,strict tilt angle incident test evaluation is required for DICE device before practical application.Finally,the large distance between adjacent MOS tubes will weaken the charge-sharing mechanism and reduce the charge collection of adjacent MOS tubes.Simulation result shows that the distance between the MOS transistors in the 55 nm process cannot be less than 1.2μm.The relevant simulation results can provide a theoretical basis and data for supporting the study of the physical mechanism of SEU and reinforcement technology,thereby promoting the application of memory d

关 键 词：双互锁存储单元 数值模拟 单粒子翻转效应 电荷共享效应 

分 类 号：TN60[电子电信—电路与系统] TP333[自动化与计算机技术—计算机系统结构]