基于FPGA的方位预滤波设计  

An Azimuth Pre-Filering Design Based on FPGA

作　　者：简育华[1] 王爱荣[1] 张金凤[1] JIAN Yuhua;WANG Airong;ZHANG Jinfeng(Xi'an Electronic Engineering Research Institute,Xi'an 710100)

机构地区：[1]西安电子工程研究所,西安710100

出　　处：《火控雷达技术》2024年第1期92-95,共4页Fire Control Radar Technology

摘　　要：本文结合某项目工程需要,介绍了一种SAR成像预滤波处理方法,在FPGA中通过外部QDRII存储芯片实现了PRT级数据流缓存,利用FPGA强大的并行处理能力完成FDC补偿以及SAR成像预滤波算法的计算,并将预滤波所有参数通过DSP控制,既缩短了运算时间,又提高了调试效率,实现了一块3U板卡完成整个SAR雷达信号处理。An SAR pre-filtering method was proposed in some paper to meet engineering requirement of some projects.The data streaming of PRT-grade in FPGA was realized via outside QDRII SDRAM caches;fdc compensation and SAR pre-filtering calculation were accomplished by using the powerful parallel processing capabilities of FPGA;all parameters with pre-filtering correlation were setting by DSP.Thanks to the above-mentioned methods,the calculating time was reduced,debugging efficiency was improved,and the SAR radar signal process in one 3U board was accomplished.

关 键 词：SAR预滤波 FDC补偿 DDR3 QDRII 

分 类 号：TN95[电子电信—信号与信息处理]