多核堆栈处理器研究与设计  

Research and design of multi-core stack processor

作　　者：刘自昂 周永录 代红兵[1,2] 刘宏杰[1,2] LIU Zi-ang;ZHOU Yong-lu;DAI Hong-bing;LIU Hong-jie(School of Information Science and Engineering,Yunnan University,Kunming 650500,China;Digital Media Technology Key Laboratory of Universities in Yunnan,Yunnan University,Kunming 650223,China)

机构地区：[1]云南大学信息学院,云南昆明650500 [2]云南大学云南省高校数字媒体技术重点实验室,云南昆明650223

出　　处：《计算机工程与设计》2024年第4期1256-1263,共8页Computer Engineering and Design

基　　金：国家自然科学基金项目(61962060)。

摘　　要：为满足日趋复杂的嵌入式环境对堆栈处理器和Forth技术的应用需求,在单核堆栈处理器模型研究的基础上,设计一种多核堆栈处理器模型。基于J1单核堆栈处理器模型,针对多核目标,增加计时器、中断等功能,形成新的L32单核堆栈处理器模型,并以该单核模型为内核,引入共享总线和十字开关互联方式的Wishbone总线、多端口存储器和面向多任务Forth系统的指令集,建立一种多核堆栈处理器模型L32-MC。利用该多核模型,在FPGA上实现4核和8核的L32-MC原型多核堆栈处理器。实验结果表明,4核和8核的L32-MC原型堆栈处理器满足高性能低功耗的多核处理器设计目标。To meet the application requirements of increasingly complex embedded environments for stack processors and Forth technologies,a multi-core stack processor model was designed based on the research of single-core stack processor model.Based on the J1 single-core stack processor model,a L32 single-core stack processor model was formed by adding timers and interrupts for multi-core target,which was taken as the core,and a multi-core stack processor model L32-MC was established by intro-ducing Wishbone bus with shared bus and cross-switch interconnection method.Using this multi-core model,the 4-core and 8-core L32-MC prototype multi-core stack processors were implemented on the FPGA.Experimental results show that the 4-core and 8-core L32-MC prototype stack processors reach the goals of high-performance and low-power multicore processor design.

关 键 词：多核堆栈处理器 Forth技术 Wishbone片上总线 多端口存储器 指令集 现场可编程门阵列 嵌入式 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]