一种低噪声、高PSRR的LDO设计  

LDO design with low noise and high PSRR

作　　者：黎佳欣 LI Jiaxin(School of Electronic and Information Engineering,Shanghai University of Electric Power,Shanghai 200120,China)

机构地区：[1]上海电力大学电子与信息工程学院,上海200120

出　　处：《电子设计工程》2024年第8期111-115,120,共6页Electronic Design Engineering

摘　　要：基于smic40工艺提出了一种低噪声、高PSRR的LDO,将在该LDO中,采用预放大结构,在传统误差放大器(EA)之前加入BJT预放大级,降低EA的1/f噪声,以提高LDO噪声性能。为了克服PSRR与其他诸如环路稳定性和负载能力等重要设计参数之间的权衡,提出的LDO使用带有二极管连接型的PMOS充当缓冲器,电源纹波通过晶体管的栅极,并通过NMOS缓冲器增强LDO的纹波抑制能力,PSRR改进超过40 dB。实验结果表明,该LDO实现了从10 Hz到100 kHz的RMS噪声在室温下小于2μV,液氮温度77 K下小于1μV;仿真在1 kHz时PSRR为-80 dB,100 kHz时PSRR为-44~-62 dB。In this paper,a low noise and high PSRR LDO based on smic40 technology is proposed.In this LDO,a pre-amplified structure is adopted and a BJT pre-amplified stage is added before the traditional Error Amplifier(EA) to reduce the 1/f noise of EA and improve the noise performance of LDO.To overcome the trade-off between the PSRR and other important design parameters such as loop stability and load capacity,the proposed LDO uses a PMOS with a diode connected type as a buffer,where the power ripple passes through the transistor's gate and the ripple suppression capability of the LDO is enhanced by an NMOS buffer,improving by more than 40 dB.Experimental results show that the LDO achieves output from 10 Hz to 100 kHz with RMS noise less than 2 μV at room temperature and less than1 μV at liquid nitrogen temperature of 77 K.The simulation PSRR is-80 dB at 1 kHz and-44 to-62 dB at 100 kHz.

关 键 词：LDO 电源抑制比 低噪声 BJT 

分 类 号：TN386.1[电子电信—物理电子学]