Post-layout simulation driven analog circuit sizing  

作　　者：Xiaohan GAO Haoyi ZHANG Siyuan YE Mingjie LIU David ZPAN Linxiao SHEN Runsheng WANG Yibo LIN Ru HUANG 

机构地区：[1]School of Integrated Circuits,Peking University,Beijing 100871,China [2]School of Computer Science,Peking University,Beijing 100871,China [3]Institute of Electronic Design Automation,Peking University,Wuxi 214000,China [4]Department of Electrical and Computer Engineering,University of Texas at Austin,Austin 78712,USA

出　　处：《Science China(Information Sciences)》2024年第4期285-296,共12页中国科学（信息科学）（英文版）

基　　金：supported in part by National Natural Science Foundation of China(Grant Nos.62141404,62034007);111 Project(Grant No.B18001)。

摘　　要：Post-layout simulation provides accurate guidance for analog circuit design,but post-layout performance is hard to be directly optimized at early design stages.Prior work on analog circuit sizing often utilizes pre-layout simulation results as the optimization objective.In this work,we propose a post-layoutsimulation-driven(post-simulation-driven for short)analog circuit sizing framework that directly optimizes the post-layout simulation performance.The framework integrates automated layout generation into the optimization loop of transistor sizing and leverages a coupled Bayesian optimization algorithm to search for the best post-simulation performance.Experimental results demonstrate that our framework can achieve over 20%better post-layout performance in competitive time than manual design and the method that only considers pre-layout optimization.

关 键 词：analog EDA transistor sizing Bayesian optimization post-layout simulation 

分 类 号：TN710[电子电信—电路与系统]