一种基于FPGA的SVPWM硬件架构及其计算速度优化  

A SVPWM Hardware Architecture Based on FPGA and Its Computational Speed Optimization

作　　者：刘德平[1] 辛云川 刘子旭 LIU Deping;XIN Yunchuan;LIU Zixu(School of Mechanical and Power Engineering,Zhengzhou University,Zhengzhou 450001,China)

机构地区：[1]郑州大学机械与动力工程学院,河南郑州450001

出　　处：《郑州大学学报（工学版）》2024年第3期96-102,共7页Journal of Zhengzhou University（Engineering Science）

基　　金：河南省重大科技专项资助项目(171100210300-01)。

摘　　要：为了提高七段式两电平SVPWM算法的调制速度并减少逻辑资源的使用量,提出了一种基于FPGA的SVPWM硬件架构。在该硬件架构输入参考电压后,首先,进行基于Clarke逆变换的坐标变换,通过一系列加法运算构建出含有三相占空比的3组中间变量,同时通过2个异或运算从上述硬件布线中得到简化后的2 bit扇区判断条件;然后,根据简化后的2 bit扇区判断条件从以上3组中间变量中筛选出三相占空比,并进行钳位保护,按照自然采样法输出PWM。以上过程形成一个整体,在FPGA中只需3次触发,便能在2个时钟周期内完成从参考电压输入到三相PWM输出的整个过程,有效提高了计算速度。此外,还给出了该硬件架构在不同的FPGA平台下的资源使用情况,与其他方法相比,LUT使用量由至少500个缩减至300个左右,逻辑资源使用量降低。通过仿真与实物试验,验证了所提硬件架构的有效性。In order to improve the modulation speed of seven segment two-level SVPWM algorithm and reduce the use of logic resources,a hardware architecture of SVPWM based on FPGA was proposed.After inputting the reference voltage,the hardware architecture first carried out the coordinate transformation based on the inverse Clarke transform,constructed three groups of intermediate variables containing three-phase duty cycle through a series of addition operations,and obtained the simplified 2 bit sector judgment conditions from the above hardware wiring through two XOR operations.Then,according to the simplified 2 bit sector judgment conditions,the three-phase duty cycle was selected from the above three groups of intermediate variables,and clamp protection was carried out,and PWM was output according to the natural sampling method.The above process formed a whole.The whole process from reference voltage input to three-phase PWM output had been completed in two clock cycles with only three triggers in FPGA,which effectively improved the calculation speed.In addition,the resource usage of the hardware architecture with different FPGA platforms was also given.Compared with other methods,the LUT usage was reduced from at least 500 to about 300,and the logical resource usage was reduced.The effectiveness of the proposed hardware architecture was verified by simulation and physical test.

关 键 词：SVPWM 硬件架构 Clarke逆变换 FPGA 计算速度优化 

分 类 号：TM464[电气工程—电器]