一种12位低功耗电阻串架构DAC  

A 12 bit Low Power Resistor-String Architecture DAC

作　　者：吴旭鹏 张理振 费宏欣 任静 周雅轩 方玉明[1] WU Xupeng;ZHANG Lizhen;FEI Hongxin;REN Jing;ZHOU Yaxuan;FANG Yuming(School of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,P.R.China;Jiangsu Runic Technology Co.,Ltd.,Nanjing 214000,P.R.China)

机构地区：[1]南京邮电大学集成电路科学与工程学院,南京210023 [2]江苏润石科技有限公司,江苏无锡214000

出　　处：《微电子学》2024年第1期32-37,共6页Microelectronics

基　　金：江苏省研究生科研与实践创新计划项目(SJCX21_0273);国家自然科学基金青年基金资助项目(11904177,61704090);南京邮电大学射频集成与微组装技术国家地方联合工程实验室开放课题(KFJJ20210205)。

摘　　要：利用分段式电阻串结构,基于CMOS工艺设计了一款12位3.4 MHz低功耗数模转换器(DAC)芯片。结合建立速度和静态性能的设计指标,确定“5+7”式分段结构,在保证建立速度的条件下考虑到电阻的失配性,实现良好的微分非线性(DNL)和积分非线性(INL)特性。后仿真结果表明,在3.4 MHz速度下,常温下DNL为0.14 LSB,INL为1 LSB,在-40~125℃下,DNL为0.6 LSB,INL为2 LSB,并且表现出-84 dB的总谐波失真(THD),以及在3 V电压下378μW的极低功耗,版图面积缩小到1.09 mm×0.91 mm。A 12-bit 3.4 MHz low power digital-to-analog converter(DAC)chip was designed in a CMOS process by using the segmented resistor string structure.Combining the design indicators of the building time and static performance,the"5+7"segmented structure was determined to realize good differential nonlinearity(DNL)and integral nonlinearity(INL)characteristics under the condition of guaranteeing the build-up speed and taking into account the mismatch of resistors.The post-simulation results show that at a speed of 3.4 MHz,the DNL is 0.14 LSB and the INL is 1 LSB at room temperature,and at-40 to 125℃,the DNL is 0.6 LSB and the INL is 2 LSB.It shows a total harmonic distortion(THD)of-84 dB and an extremely low power consumption of 378μW at 3 V voltage.The layout area is reduced to 1.09 mm×0.91 mm.

关 键 词：数模转换器 分段结构 低功耗 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792