高压GGNMOS器件结构及工艺对ESD防护特性的影响  

Effect of Layout and Process on ESD Characteristics of High-voltage GGNMOS

作　　者：傅凡 万发雨[1] 汪煜 洪根深 FU Fan;WAN Fayu;WANG Yu;HONG Genshen(School of Electronic&Information Engineering,Nanjing University of Information Science&Technology,Nan-jing,210000,CHN;The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi,Jiangsu,214072,CHN)

机构地区：[1]南京信息工程大学电子与信息工程学院,南京210000 [2]中国电子科技集团公司第五十八研究所,江苏无锡214072

出　　处：《固体电子学研究与进展》2024年第2期178-182,共5页Research & Progress of SSE

基　　金：国家重点研发计划资助项目(2022YFE0122700);北京东方计量测试研究所刘尚合院士专家工作站静电研究基金资助项目(BOIMTLSHJD20221004)。

摘　　要：基于高压CMOS工艺,对高压栅极接地N型金属氧化物半导体(Highvoltagegrounded-gate N-metal-oxide-semiconductor, HV-GGNMOS)的静电放电(Electrostatic discharge, ESD)防护性能进行研究。由于强折回特性以及失效电流低,HV-GGNMOS在实际应用中受到限制。本文通过计算机辅助设计技术仿真及传输线脉冲实验研究了工艺参数及版图结构对器件ESD防护性能的影响。结果表明,增加漂移区掺杂浓度可以有效提高器件失效电流;加强体接触和增加漂移区长度可以提高器件的维持电压,但失效电流会有所下降,占用版图面积也会更大。Based on high voltage CMOS technology,the electrostatic discharge(ESD)protec-tion performance of high voltage grounded-gate N-metal-oxide-semiconductor(HV-GGNMOS)ESD devices was studied.Due to its strong snapback and low failure current,HV-GGNMOS is limited in practical applications.In this paper,the effect of doping profiles and layout structure on ESD protec-tion performance of the device were analyzed by TCAD simulation and transmission line pulse experi-ment.The results indicate that the device failure current can be effectively improved by increasing the doping concentration in the drift region.The holding voltage can be increased by strengthening the body contact and increasing the length of drift region,but the failure current will decrease,and the lay-out area will also be larger.

关 键 词：静电放电防护 栅极接地NMOS 维持电压 失效电流 

分 类 号：TN386[电子电信—物理电子学]