面向国产处理器的FPGA原型验证系统优化方法  

Optimization Method of FPGA Prototype Verification System for Domestic Processor

作　　者：褚捃博 CHU Junbo(Information Engineering University,Zhengzhou 450001,China)

机构地区：[1]信息工程大学,河南郑州450001

出　　处：《信息工程大学学报》2024年第2期155-161,共7页Journal of Information Engineering University

摘　　要：在集成电路的设计过程中,流片之前进行现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)验证是一个必不可少的环节。在对某款国产处理器芯片进行FPGA验证时,一些性能测试课题出现测试结果不稳定,与其他验证平台结果出入较大的现象。针对这一问题,基于事务处理模块开发了一套新型调试系统,能够方便准确地观测到FPGA测试过程中关键事务的动态变化数据,并实时传递。用事务级查错方式替代常见的信号级查错手段,有效提高了FPGA原型验证过程的可观测性,加快问题定位速度,提高查错验证效率。在目标处理器芯片验证流程中,成功解决二级缓存访存延迟测试不稳定的问题,取得了一定成效。Field programmable gate array(FPGA)verification is a necessary step in the design of integrated circuits.In the FPGA verification of a home-made processor chip,the test results of some performance test subjects are unstable,and the results differ greatly from those of other verification platforms.To solve this problem,a new debugging system based on transaction processing module is developed,which can easily and accurately observe the dynamic changes of key transactions in FPGA testing process and real-time transmission.Using transaction-level error checking method instead of common signal-level error checking method,the observability of FPGA prototype verification process is effectively improved,the speed of problem location is accelerated,and the efficiency of error checking and verification is improved.In the verification process of the target processor chip,the problem of unstable testing of the second-level cache memory access delay has been successfully solved,and some achievements have been made.

关 键 词：FPGA原型验证 FPGA调试方法 事务处理模块 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]