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作 者:牛志强 陈志坤 胡子阳[1] 王刚[1] 刘剑[2,3] 吴南健 冯鹏[2,3] NIU Zhiqiang;CHEN Zhikun;HU Ziyang;WANG Gang;LIU Jian;WU Nanjian;FENG Peng(School of Physical Science and Technology,Ningbo University,Ningbo 315211,China;State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;Center of Materials Science and Optoelectronics Engineering,University of Chinese Academy of Sciences,Beijing 100049,China)
机构地区:[1]宁波大学物理科学与技术学院,宁波315211 [2]中国科学院半导体研究所半导体超晶格国家重点实验室,北京100083 [3]中国科学院大学材料与光电研究中心,北京100049
出 处:《集成电路与嵌入式系统》2024年第5期48-54,共7页INTEGRATED CIRCUITS AND EMBEDDED SYSTEMS
基 金:国家自然科学基金重点项目(62134004)。
摘 要:针对高帧率CMOS图像传感器的应用需求,提出一种结合逐次逼近型(Successive Approximation Register,SAR)和单斜坡(Single Slope,SS)结构的混合型模拟数字转换器(Analog to Digital Converter,ADC)。该ADC的分辨率为12位,其中SAR ADC实现高6位量化,SS ADC实现低6位量化。该ADC采用了全差分结构消除采样开关的固定失调并减少非线性误差,同时在SAR ADC中采用了异步逻辑电路进一步缩短转换周期。采用110 nm 1P4M CMOS工艺对该电路进行了设计和版图实现,后仿真结果表明,在20 MHz的时钟下,转换周期仅为3.3μs,无杂散动态范围为77.12 dB,信噪失真比为67.38 dB,有效位数为10.90位。Aiming at the application requirements of high frame rate CMOS image sensors,a hybrid analog-to-digital converter(ADC)combining successive approximation register(SAR)and single slope(SS)structures is proposed.The resolution of this ADC is 12 bit,with SAR ADC achieving high 6-bit quantization and SS ADC achieving low 6-bit quantization.The ADC adopts a fully differential structure to eliminate fixed misalignment of the sampling switch and reduce nonlinear errors.At the same time,asynchronous logic circuits are used in SAR ADC to further shorten the conversion cycle.The circuit is designed and implemented using 110 nm 1P4M CMOS technology.The post-layout simulation results show that at clock frequency of 20 MHz,the conversion period is only 3.3μs,the spurious free dynamic range is 77.12 dB,the signal-to-noise distortion ratio is 67.38 dB,and the effective bit is 10.90 bits.
关 键 词:高帧率CMOS图像传感器 混合型列ADC 单斜ADC 逐次逼近型ADC 电流舵DAC
分 类 号:TN43[电子电信—微电子学与固体电子学]
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