基于IEEE 802.1AS的多跳时钟同步算法与系统实现  

Multi-Hop Clock Synchronization Algorithm and System ImplementationBased on IEEE 802.1AS

作　　者：赵国锋[1] 危瑞鹏 邢媛 徐川[1] 张汝凤 ZHAO Guo-feng;WEI Rui-peng;XING Yuan;XU Chuan;ZHANG Ru-feng(School of Communications and Information Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065,China)

机构地区：[1]重庆邮电大学通信与信息工程学院,重庆400065

出　　处：《电子学报》2024年第3期814-823,共10页Acta Electronica Sinica

基　　金：国家自然科学基金(No.62171070);国家重点研发计划项目(No.2018YFB1800301,No.2018YFB1800304);重庆市研究生科研创新项目(No.CYB19176);重庆邮电大学博士研究生人才培养项目(No.BYJS201905)。

摘　　要：针对现有IEEE 802.1AS协议中单一主时钟无法保障多跳网络下高精度同步的问题,提出一种基于多属性决策的冗余时钟同步方法.首先,基于链路拥塞程度、节点拓扑属性和时钟源质量系数对时钟属性值进行建模;其次,采用多属性决策算法选取最佳主时钟并生成冗余时钟序列表;最后,利用FPGA(Field Programmable Gate Array)平台设计并实现冗余时钟同步系统,同时搭建真实网络环境对所提方法进行测试.结果表明,相较于现有方法,时钟同步精度提升了68%,主时钟失效后重新同步所需收敛时间减小了60%.Aiming at the problem that a single master clock in the existing IEEE 802.1AS protocol cannot guarantee the high precision of clock synchronization in multi-hop network,a redundant clock synchronization method based on multiattribute decision-making is proposed.Firstly,the clock attribute value is modeled based on the link congestion degree,to⁃pology attribute of node and clock source quality factor.Secondly,the multi-attribute decision-making algorithm is used to select the best master clock and generate a redundant clock sequence table;Finally,the redundant clock synchronization sys⁃tem is designed and implemented on field programmable gate array(FPGA)platform,and a real network environment is constructed to test the proposed method.The results show that,compared with the existing methods,the clock synchroniza⁃tion accuracy is improved by 68%,and the convergence time required for resynchronization after master clock failure is re⁃duced by 60%.

关 键 词：时钟同步 IEEE 802.1AS协议 主时钟选取 冗余时钟 FPGA 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]