基于FPGA的LVDS总线控制器的设计与实现  

Design and Implementation of LVDS Bus Controller Based on FPGA

作　　者：文丰[1] 黄浩然 贾兴中[1] WEN Feng;HUANG Haoran;JIA Xingzhong(Key Laboratory of Instrument Science and Dynamic Testing,North University of China,Ministry of Education,Taiyuan 030051)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《舰船电子工程》2024年第2期214-218,共5页Ship Electronic Engineering

摘　　要：为保证在高速、多负载条件下LVDS总线的运行状态和传输速率满足应用需求,基于FPGA设计LVDS总线控制器,协议上优化了LVDS的总线占用方式、信号传输逻辑,并在物理层优化了总线结构以及节点接口。为防止低压差分信号失真以及接口失锁问题,采取信号编码和失锁预防措施,保证信号的稳定,增强总线的可靠性。经验证,该方案可提高总线带负载能力,保持高速率下的可靠传输。In order to ensure that the operation status and transmission rate of LVDS bus meet the application requirements un⁃der high-speed and multi-load conditions,the LVDS bus controller is designed based on FPGA.The bus occupation mode and sig⁃nal transmission logic of LVDS are optimized in the protocol,and the bus structure and node interface are optimized in the physical layer.In order to prevent low voltage differential signal distortion and interface lock-out,signal coding and lock-out prevention mea⁃sures are taken to ensure signal stability and enhance the reliability of the bus.It is verified that the scheme can improve the load ca⁃pacity of the bus and maintain reliable transmission at high speed.

关 键 词：LVDS 总线 8b/10b编码 FPGA 

分 类 号：TP216[自动化与计算机技术—检测技术与自动化装置]