10 bit高速低功耗SAR ADC设计  

A 10 bit High Speed Low Power SAR ADC Design

作　　者：段鉴容 聂海[1] DUAN JianRong;NIE Hai(College of Communication Engineering,Chengdu University of Information Technology,Chengdu 610225,China)

机构地区：[1]成都信息工程大学通信工程学院,四川成都610225

出　　处：《成都信息工程大学学报》2024年第1期13-17,共5页Journal of Chengdu University of Information Technology

基　　金：四川省科技项目重点研发资助项目(2022YFG003)。

摘　　要：基于TSMC40 nm工艺,提出一种高速低功耗逐次逼近型模数转换器。设计电路采用全差分结构,基于vcm-based电容拆分技术解决先进工艺下难以设计精准VCM电平和复杂逻辑的问题,采用double-tail动态比较器实现高速和低功耗,采用TSPC触发器设计SAR逻辑进一步提高速度和降低功耗,采用异步时序,通过环路自身产生比较器时钟,不需要外接时钟信号,降低设计复杂度。在150 MHz采样频率,1.1 V电源电压,奈奎斯特的输入频率下,对该设计进行仿真,仿真结果表明,SAR ADC的ENOB=9.93 bit,SNDR=61.6 dB,SFDR=78.6 dB。Based on the TSMC40nm process,this paper proposes a high-speed,low-power successive approximation analog-to-digital converter(ADC)with advanced circuit design features.The proposed ADC overcomes the challenges associated with precise VCM levels and complex logic in advanced processes by employing a fully differential structure and a vcm-based capacitor splitting technique.Furthermore,a double-tail dynamic comparator achieves high speed and low power consumption,while a TSPC trigger optimizes the SAR logic for speed and power.An asynchronous timing scheme generates comparator clocks through the loop itself,avoiding the need for an external clock signal and simplifying the design.Simulation results at a sampling frequency of 150 MHz,a supply voltage of 1.1 V,and an input frequency nearly the Nyquist frequency show that the SAR ADC has an ENOB of 9.93 bit,an SNDR of 61.6 dB,and an SFDR of78.6 dB.

关 键 词：SAR ADC 高速 低功耗 电容拆分技术 

分 类 号：TN402[电子电信—微电子学与固体电子学]